The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a Lateral Double-Diffused MOSFET (LDMOS), comprising: providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; applying a first ion implantation using a mask on the semiconductor substrate to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure, wherein the second conductivity type is opposite of the first conductivity type; applying a second ion implantation using the same mask to form a first doped region in the semiconductor substrate such that the first doped region includes a first portion and a second portion that are connected, wherein the first portion is located in the drift region surrounding the STI structure, the second portion is located in the semiconductor substrate outside the drift region and under a gate structure to be subsequently formed, and a depth of the first doped region is less than a depth of the drift region; applying a counter-doping implantation using the same mask to form a counter-doped region surrounding the STI structure and having the first conductivity in the drift region, wherein a depth of the counter-doped region is less than the depth of the drift region; after forming the counter-doped region, forming a body region on one side of the drift region in the semiconductor substrate, wherein the body region has the first conductivity type; and forming the gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.
2. The method according to claim 1 , wherein: the first doped region is doped with dopants of the second conductivity.
3. The method according to claim 1 , wherein the LDMOS is an N-type LDMOS, the dopants of the first conductivity type are P-type dopants, and the dopants of the second conductivity type are N-type dopants.
4. The method according to claim 1 , wherein the LDMOS is a P-type LDMOS, the dopants of the first conductivity type are N-type dopants, and the dopants of the second conductivity type are P-type dopants.
5. The method according to claim 1 , further including: forming a drain region in the drift region on one side of the first STI structure facing away from the gate structure and doped with dopants of the second conductivity type, the drain region overlapping with a portion of the counter-doped region on the one side of the first STI structure facing away from the gate structure; and forming a source region in the body region on one side facing the gate structure and doped with dopants of the second conductivity type.
6. The method according to claim 1 , wherein the gate structure includes a gate dielectric on the semiconductor substrate, a gate electrode on the gate dielectric, and sidewalls on both sides of the gate electrode and the gate dielectric.
7. The method according to claim 2 , wherein the depth of the counter-doped region is less than the depth of the first doped region.
8. The method according to claim 2 , wherein a formation process of the drift region includes: forming a mask layer having an opening to expose a portion of the semiconductor substrate; and applying the mask layer as the same mask for the first ion implantation to dope dopants of the second conductivity type into the semiconductor substrate to form the drift region to surround the first STI structure.
9. The method according to claim 3 , wherein the P-type dopants are one or more of boron ions, indium ions, and gallium ions, and the N-type dopants are one or more of phosphorus ions, arsenic ions, and antimony ions.
10. The method according to claim 5 , wherein a depth of the drain region is greater than the depth of the counter-doped region.
11. The method according to claim 7 , wherein a tilt angle of the second ion implantation is about 15° to about 45°, an ion implantation energy is about 150 KeV to about 250 KeV, and an ion dose is about 1E12 atom/cm 2 to about 1.5E13 atom/cm 2 .
12. The method according to claim 7 , wherein a tilt angle of the counter-doping ion implantation is about 0° to about 7°, an ion implantation energy is about 30 KeV to about 100 KeV, and an ion dose is about 1E12 atom/cm 2 to about 1.5E13 atom/cm 2 .
13. The method according to claim 7 , wherein the first ion implantation further includes a first-step ion implantation and a second-step ion implantation, wherein: a tilt angle of the first-step ion implantation is about 0° to about 7°, an ion implantation energy is about 500 KeV to about 1M KeV, and an ion dose is about 5E11 atom/cm 2 to about 1E13 atom/cm 2 ; and a tilt angle of the second-step ion implantation is about 0° to about 7°, an ion implantation energy is about 250 KeV to about 500 KeV, and an ion dose is about 5E11 atom/cm 2 to about 1E13 atom/cm 2 .
14. The method according to claim 8 , wherein formation processes of the first doped region and the counter-doped region include: applying the mask layer as the same mask for the second ion implantation to dope dopants of the second conductivity into the semiconductor substrate to form the first doped region, wherein the first doped region includes the connected first portion and second portion, the first portion is located in the drift region, the second region is located in the semiconductor substrate outside the drift region and under the gate structure, and the depth of the first doped region is less than the depth of the drift region; applying the mask layer as the same mask for the counter-doping ion implantation to dope dopants of the first conductivity type into the drift region to form the counter-doping region having a depth less than the depth of the drift region.
15. An LDMOS (Lateral-Double-Diffused MOSFET), comprising: a semiconductor substrate having a first conductivity type; a first shallow trench isolation (STI) structure in the semiconductor substrate; a drift region having a second conductivity type, in the semiconductor substrate and surrounding the first STI structure, wherein the second conductivity type is opposite of the first conductivity type; a counter-doped region having the first conductivity type and in the drift region, the counter-doped region being partially located under a gate structure and surrounding the STI structure, wherein a depth of the counter-doped region is less than a depth of the drift region; a first doped region in the semiconductor substrate having the second conductivity type, the first doped region including a first portion and a second portion that are connected, the first portion being located in the drift region surrounding the STI structure, the second portion being located in the semiconductor substrate outside the drift region and under a gate structure to be subsequently formed, and a depth of the first doped region being greater than the depth of the counter-doped region and less than the depth of the drift region; a body region having the first conductivity type and on one side of the drift region in the semiconductor substrate; and the gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region and another end of the gate structure extends to an area on the first STI structure.
16. The LDMOS according to claim 15 , wherein a doping concentration of the dopants of the first conductivity type is about 1E12 atom/cm3 to about 1.5E13 atom/cm3 in the counter-doped region; a doping concentration of the dopants of the second conductivity type is about 1E12 atom/cm3 to about 1.5E13 atom/cm3 in the first doped region; and a doping concentration of the dopants of the second conductivity type is about 5E11 atom/cm3 to about 1E13 atom/cm3 in the drift region.
17. The LDMOS according to claim 15 , wherein the LDMOS is an N-type LDMOS, the dopants of the first conductivity type are P-type dopants, and the dopants of the second conductivity type are N-type dopants.
18. The LDMOS according to claim 15 , wherein the LDMOS is a P-type LDMOS, the dopants of the first conductivity type are N-type dopants, and the dopants of the second conductivity type are P-type dopants.
19. The LDMOS according to claim 15 , wherein the LDMOS is one of an N-type LDMOS and a P-type LDMOS.
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June 12, 2015
January 3, 2017
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