A circuit for generation of a reference voltage for an electronic system, which circuit comprises at least one digital buffer (U21, U31, U32, U41, U51), a low pass filter (R21, C21; R31, C31; R41, C41; R51, C51) and an operational amplifier (OA21, OA31, OA41, OA51)), which circuit is adapted to revive an input in the form of a bandgap reference voltage into the digital buffer, which digital buffer is adapted to receive a digital input from a Pulse Width Modulated (PWM) signal, which digital buffer is adapted to generate an output signal adapted to be fed to the low pass filter, which output signal after filtration is adapted to be fed to a positive input terminal of the operational amplifier, which operational amplifier comprises a feedback circuit, which feedback circuit comprises at least one capacitor (C22, C32, C44, C54) adapted to be connected from an output terminal of the operational amplifier towards a negative input terminal of the operational amplifier so as to form an integrator, wherein the feedback circuit further comprises at least one chopped signal path (R22, S21; R33, R34, S32; R33, R35, C35, S31), which chopped signal is adapted to be modulated by the output signal of the digital buffer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit for generation of a reference voltage for an electronic system, which circuit comprises at least one digital buffer (U 21 , U 31 , U 32 , U 41 , U 51 ), a low pass filter (R 21 , C 21 ; R 31 , C 31 ; R 41 , C 41 ; R 51 , C 51 ) and an operational amplifier (OA 21 , OA 31 , OA 41 , OA 51 ), which circuit is adapted to revive an input in the form of a bandgap reference voltage into the digital buffer, which digital buffer is adapted to receive a digital input from a Pulse Width Modulated (PWM) signal, which digital buffer is adapted to generate an output signal adapted to be fed to the low pass filter, which output signal after filtration is adapted to be fed to a positive input terminal of the operational amplifier, which operational amplifier comprises a feedback circuit, which feedback circuit comprises at least one capacitor (C 22 , C 32 , C 44 , C 54 ) adapted to be connected from an output terminal of the operational amplifier towards a negative input terminal of the operational amplifier so as to form an integrator, whereby the feedback circuit further comprises at least one chopped signal path (R 22 , S 21 ; R 33 , R 34 , S 32 ; R 33 , R 35 , C 35 , S 31 ), which chopped signal is adapted to be modulated by the output signal of the digital buffer.
2. The circuit for generation of the reference voltage according to claim 1 , wherein the feedback circuit comprises two individual out of phase chopped signal paths, wherein one signal path (R 33 , R 34 , S 32 ) is adapted to determine a direct current of an output voltage and the other signal path (R 33 , R 35 , C 35 , S 31 ) is adapted to cancel the triangular signal behaviour of the operational amplifier due to the currents flowing in the two paths in opposite directions.
3. The circuit for generation of the reference voltage according to claim 2 , wherein the operational amplifier (OA 21 , OA 31 , OA 41 , OA 51 ) is a zero-drift operational amplifier adapted to eliminate the temperature drift of an offset voltage drift of the operational amplifier.
4. The circuit for generation of the reference voltage according to claim 3 , wherein a single pole dual throw switch (S 41 ) is adapted to perform the chopping of the signal paths.
5. The circuit for generation of the reference voltage according to claim 2 , wherein two MOSFET transistors (M 51 , M 52 ) are adapted to perform the chopping of the two signal paths.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 8, 2016
January 24, 2017
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