Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a first resist-mask on top of a first portion of the hard-mask layer and applying the first resist-mask in forming a first type of wells in a first region of the substrate; forming a second resist-mask on top of a second portion of the hard-mask layer and applying the second resist-mask in forming a second type of wells in a second region of the substrate; applying the first and second resist-masks in transforming the hard-mask layer into a hard-mask, the hard-mask having openings aligned to areas overlapped by the first and second regions of the substrate; etching at least the areas of the substrate in creating deep trenches that separate the first and second types of wells; and filling the deep trenches with insulating materials.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method comprising: forming a first resist mask directly on top of a first hard mask layer and above a first region of a semiconductor substrate; removing a portion of the first hard mask layer selective to the first resist mask and selective to a second hard mask layer beneath the first hard mask layer; forming a first type well in a second region of the semiconductor substrate not covered by the first resist mask; forming a second resist mask directly on top of the second hard mask layer and above the second region of the semiconductor substrate; forming an opening in the second hard mask layer selective to the second resist mask and a remaining portion of the first hard mask layer; forming a second type well in the first region of the semiconductor substrate, the second type well at least partially overlapping the first type well in a third region of the semiconductor substrate; expanding the opening in the second hard mask layer horizontally using an isotropic etching process selective to the remaining portion of the first hard mask layer and selective to the second resist mask; etching a deep trench in the third region of the semiconductor substrate, the deep trench separates the first type well from the second type of well; and filling the deep trench with insulating materials.
2. The method of claim 1 , wherein etching the deep trench in the third region of the semiconductor substrate comprises: etching areas of the semiconductor substrate exposed by expanding the opening in the second hard mask layer.
3. The method of claim 1 , wherein the first type well is implanted with negative ions and the second type well is implanted with positive ions.
4. The method of claim 1 , wherein forming the opening in the second hard mask layer selective to the second resist mask and the remaining portion of the first hard mask layer comprises: selectively etching the second hard mask layer in areas that are neither covered by the remaining portion of the first hard mask layer nor covered by the second resist mask until an upper surface of the semiconductor substrate underneath the second hard mask layer is exposed.
5. The method of claim 1 , wherein the first hard mask layer is materially different from the second hard mask layer and has different etch selectivity.
6. The method of claim 1 , wherein forming the first type well in the second region of the semiconductor substrate comprises: performing a first ion implantation in the second region of the semiconductor substrate that is not covered by the first resist mask.
7. The method of claim 1 , wherein forming the second type well in the first region of the semiconductor substrate comprises: performing a second ion implantation in the first region of the semiconductor substrate that is not covered by the second resist mask.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 8, 2016
January 31, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.