The invention provides a thin film transistor substrate includes: a substrate; and a plurality of transistors, wherein each of the transistors includes a gate electrode disposed on the substrate; a first diffusion barrier layer disposed on the substrate and covering an upper surface and a ring sidewall of the gate electrode; a gate insulating layer disposed on the first diffusion barrier layer; an active layer disposed on the gate insulating layer and over the gate electrode; a source electrode disposed on the substrate and electrically connected to the active layer; a drain electrode disposed on the substrate and electrically connected to the active layer; and a protective layer covering the source electrode and the drain electrode.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A thin film transistor substrate, comprising: a substrate; and a plurality of thin film transistors disposed on the substrate, wherein each of the thin film transistors comprises: a gate electrode disposed on the substrate; a first layer disposed on the gate electrode and comprising silicon nitride; a second layer disposed on the first layer and comprising silicon oxide, wherein a hydrogen content of the first layer is greater than a hydrogen content of the second layer; a metal oxide layer disposed on the second layer and over the gate electrode; a source electrode disposed on the substrate and electrically connected to the metal oxide layer; a drain electrode disposed on the substrate and electrically connected to the metal oxide layer; and a protective layer covering the source electrode and the drain electrode.
2. The thin film transistor substrate as claimed in claim 1 , wherein the metal oxide layer comprises indium gallium zinc oxide.
3. The thin film transistor substrate as claimed in claim 1 , wherein each of the thin film transistors further comprises a bottom layer formed between the substrate and the gate electrode.
4. The thin film transistor substrate as claimed in claim 1 , wherein each of the thin film transistors further comprises a bottom layer formed between the source electrode and the metal oxide layer, and between the drain electrode and the metal oxide layer.
5. The thin film transistor substrate as claimed in claim 1 , wherein a thickness of the first layer is greater than a thickness of the second layer.
6. The thin film transistor substrate as claimed in claim 5 , wherein the thickness of the second layer is about 500 angstroms to 1000 angstroms.
7. A display, comprising: a thin film transistor substrate; a substrate disposed opposite to the thin film transistor substrate; and a display medium disposed between the thin film transistor substrate and the substrate; wherein the thin film transistor substrate comprises: a substrate; and a plurality of thin film transistors disposed on the substrate, wherein each of the thin film transistors comprises: a gate electrode disposed on the substrate; a first layer disposed on the gate electrode and comprising silicon nitride; a second layer disposed on the first layer and comprising silicon oxide, wherein a hydrogen content of the first layer is greater than a hydrogen content of the second layer; a metal oxide layer disposed on the second layer and over the gate electrode; a source electrode disposed on the substrate and electrically connected to the metal oxide layer; a drain electrode disposed on the substrate and electrically connected to the metal oxide layer; and a protective layer covering the source electrode and the drain electrode.
8. The display as claimed in claim 7 , wherein the display medium is a liquid crystal layer.
9. The display as claimed in claim 7 , wherein the display medium is an organic light emitting layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 9, 2016
January 31, 2017
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