The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.
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1. An amplifier comprising: a first transistor configured to receive a first input; a second transistor configured to receive a second input; and a plurality of impedance networks coupled between the first transistor and the second transistor, at least one impedance network of the plurality of impedance networks comprising: a first impedance path configured to be activated during single ended operation, the first impedance path including a first impedance coupled between a terminal of the first transistor and a first node, and a first switch coupled between the first node and a terminal of the second transistor; and a second impedance path configured to be activated during differential operation, the second impedance path including a second impedance coupled between the terminal of the first transistor and a second node, a second switch coupled between the second node and a third node, and a third impedance coupled between the third node and the terminal of the second transistor.
An amplifier has a first transistor receiving a first input and a second transistor receiving a second input. Multiple impedance networks connect the two transistors. At least one impedance network has two paths. The first path, with a first impedance and a first switch, activates during single-ended operation. The first impedance sits between a terminal of the first transistor and a first node, while the first switch sits between the first node and a terminal of the second transistor. The second path, with a second impedance, a second switch, and a third impedance, activates during differential operation. The second impedance sits between the same terminal of the first transistor and a second node. The second switch sits between the second node and a third node. The third impedance sits between the third node and the terminal of the second transistor.
2. The amplifier of claim 1 , wherein the first input is greater than the second input during the single ended operation.
The amplifier described as having a first transistor receiving a first input, a second transistor receiving a second input, and a plurality of impedance networks, where at least one impedance network includes a first impedance path with a first impedance and a first switch for single-ended operation, and a second impedance path with a second and third impedance and a second switch for differential operation, has the first input being greater than the second input during single-ended operation.
3. The amplifier of claim 1 , wherein the first input and the second input are differential signals during the differential operation.
The amplifier described as having a first transistor receiving a first input, a second transistor receiving a second input, and a plurality of impedance networks, where at least one impedance network includes a first impedance path with a first impedance and a first switch for single-ended operation, and a second impedance path with a second and third impedance and a second switch for differential operation, has the first and second inputs being differential signals during differential operation.
4. The amplifier of claim 1 , wherein the first transistor is an NPN transistor whose base terminal is configured to receive the first input, whose first terminal is an emitter terminal that is coupled to the plurality of impedance networks and whose collector terminal is coupled to a power supply through a first load resistor.
The amplifier described as having a first transistor receiving a first input, a second transistor receiving a second input, and a plurality of impedance networks, where at least one impedance network includes a first impedance path with a first impedance and a first switch for single-ended operation, and a second impedance path with a second and third impedance and a second switch for differential operation, has the first transistor as an NPN transistor. Its base receives the first input, its emitter connects to the impedance networks, and its collector connects to a power supply through a first load resistor.
5. The amplifier of claim 4 , further comprising a first biasing current source coupled between the emitter terminal of the first transistor and a ground terminal.
The amplifier, with an NPN transistor whose base receives the first input, whose emitter connects to the impedance networks, and whose collector connects to a power supply through a first load resistor, further includes a first biasing current source between the first transistor's emitter and ground.
6. The amplifier of claim 1 , further comprising: a first output node coupled between the first load resistor and the collector terminal of the first transistor, wherein a first output is generated at the first output node; and a second output node coupled between the second load resistor and the collector terminal of the second transistor, wherein a second output is generated at the second output node.
The amplifier described as having a first transistor receiving a first input, a second transistor receiving a second input, and a plurality of impedance networks, where at least one impedance network includes a first impedance path with a first impedance and a first switch for single-ended operation, and a second impedance path with a second and third impedance and a second switch for differential operation, also includes a first output node between the first load resistor and the first transistor's collector, generating a first output. It further includes a second output node between the second load resistor and the second transistor's collector, generating a second output.
7. The amplifier of claim 1 , wherein during the single ended operation, the first switch is activated and the second switch is inactivated such that a voltage swing across the first switch is less than a voltage swing across the second switch.
In the amplifier described as having a first transistor receiving a first input, a second transistor receiving a second input, and a plurality of impedance networks, where at least one impedance network includes a first impedance path with a first impedance and a first switch for single-ended operation, and a second impedance path with a second and third impedance and a second switch for differential operation, during single-ended operation, the first switch is activated, and the second switch is inactivated. The voltage swing across the first switch is therefore less than the voltage swing across the second.
8. The amplifier of claim 1 , wherein during the single ended operation, each of the first switch and the second switch is inactivated such that a voltage swing across both the first switch and the second switch is equal.
In the amplifier described as having a first transistor receiving a first input, a second transistor receiving a second input, and a plurality of impedance networks, where at least one impedance network includes a first impedance path with a first impedance and a first switch for single-ended operation, and a second impedance path with a second and third impedance and a second switch for differential operation, during single-ended operation, both the first and second switches are inactivated, meaning that the voltage swing across both switches is equal.
9. The amplifier of claim 1 , wherein during the differential operation, the first switch is inactivated and the second switch is activated such that a voltage swing across the second switch is less than a voltage swing across the first switch.
In the amplifier described as having a first transistor receiving a first input, a second transistor receiving a second input, and a plurality of impedance networks, where at least one impedance network includes a first impedance path with a first impedance and a first switch for single-ended operation, and a second impedance path with a second and third impedance and a second switch for differential operation, during differential operation, the first switch is inactivated and the second switch is activated. The voltage swing across the second switch is therefore less than the voltage swing across the first switch.
10. The amplifier of claim 1 , wherein during the differential operation, each of the first switch and the second switch is inactivated such that a voltage swing across both the first switch and the second switch is equal.
In the amplifier described as having a first transistor receiving a first input, a second transistor receiving a second input, and a plurality of impedance networks, where at least one impedance network includes a first impedance path with a first impedance and a first switch for single-ended operation, and a second impedance path with a second and third impedance and a second switch for differential operation, during differential operation, both the first and second switches are inactivated, making the voltage swing across both switches equal.
11. An amplifier comprising: a first transistor configured to receive a first input; a second transistor configured to receive a second input; and a plurality of impedance networks coupled between the first transistor and the second transistor, at least one impedance network of the plurality of impedance networks comprising: a first impedance path configured to be activated during single ended operation; and a second impedance path configured to be activated during differential operation, wherein the second transistor is an NPN transistor whose base terminal is configured to receive the second input, whose emitter terminal is coupled to the plurality of impedance networks and whose collector terminal is coupled to a power supply through a second load resistor.
An amplifier has a first transistor receiving a first input and a second transistor receiving a second input. Multiple impedance networks connect the two transistors. At least one impedance network has two paths: a first impedance path activated during single-ended operation, and a second impedance path activated during differential operation. The second transistor is an NPN transistor, with its base terminal receiving the second input, its emitter connected to the impedance networks, and its collector connected to a power supply through a second load resistor.
12. The amplifier of claim 11 , further comprising a second biasing current source coupled between the emitter terminal of the second transistor and the ground terminal.
The amplifier, with an NPN transistor whose base receives the second input, whose emitter connects to the impedance networks, and whose collector connects to a power supply through a second load resistor, and a plurality of impedance networks, where at least one impedance network includes a first impedance path for single ended operation and a second impedance path for differential operation, also includes a second biasing current source between the second transistor's emitter and ground.
13. A method comprising: providing a first input and a second input to an amplifier, the amplifier including an impedance network; activating a first impedance path in the impedance network during single ended operation, the first impedance path including a first switch; and activating a second impedance path in the impedance network during differential operation, the second impedance path including a second switch, wherein during the single ended operation the first switch is activated and the second switch is inactivated such that a voltage swing across the first switch is less than a voltage swing across the second switch.
A method involves providing first and second inputs to an amplifier containing an impedance network. A first impedance path within the network, including a first switch, is activated during single-ended operation. A second impedance path, including a second switch, is activated during differential operation. During single-ended operation, the first switch is activated while the second switch is inactivated, resulting in a lower voltage swing across the first switch compared to the second.
14. The method of claim 13 further comprising configuring the first input to be greater than the second input during the single ended operation, and configuring the first input and the second input as differential signals during the differential operation.
The method of providing first and second inputs to an amplifier containing an impedance network; activating a first impedance path with a first switch during single-ended operation; and activating a second impedance path with a second switch during differential operation, has further steps. The first input is configured to be greater than the second input during single-ended operation. The first and second inputs are configured as differential signals during differential operation.
15. The method of claim 13 further comprising inactivating the first switch and the second switch during the single ended operation and during the differential operation such that a voltage swing across both the first switch and the second switch is equal.
The method of providing first and second inputs to an amplifier containing an impedance network; activating a first impedance path with a first switch during single-ended operation; and activating a second impedance path with a second switch during differential operation, further includes a step: The first and second switches are inactivated during both single-ended and differential operation, creating an equal voltage swing across both switches.
16. A receiver comprising: a receive antenna configured to receive a signal and configured to generate a first input and a second input; an amplifier coupled to the receive antenna, the amplifier comprising: a first transistor configured to receive the first input; a second transistor configured to receive the second input; and a plurality of impedance networks coupled between the first transistor and the second transistor, at least one impedance network of the plurality of impedance networks comprising: a first impedance path configured to be activated during single ended operation, the first impedance path including a first impedance coupled between a terminal of the first transistor and a first node, and a first switch coupled between the first node and a terminal of the second transistor; and a second impedance path configured to be activated during differential operation, the second impedance path including a second impedance coupled between the terminal of the first transistor and a second node, a second switch coupled between the second node and a third node, and a third impedance coupled between the third node and the terminal of the second transistor; an IF filter coupled to the amplifier and configured to generate a filtered non-zero IF signal from a signal received from the amplifier; an analog to digital converter (ADC) coupled to the IF filter and configured to sample the filtered non-zero IF signal to generate a valid data; and a processor coupled to the ADC and configured to process the valid data.
A receiver includes a receive antenna which receives a signal and generates a first and second input; and an amplifier. The amplifier contains a first transistor which receives the first input; a second transistor which receives the second input; and a plurality of impedance networks coupled between the transistors. At least one network has two paths. The first path activates during single-ended operation, containing a first impedance between a terminal of the first transistor and a first node, and a first switch between the first node and a terminal of the second transistor. The second path activates during differential operation, and contains a second impedance between the first transistor's terminal and a second node, a second switch between the second node and a third node, and a third impedance between the third node and the second transistor's terminal. An IF filter filters a non-zero IF signal from the amplifier output. An ADC samples the filtered signal to generate valid data. A processor processes the valid data.
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September 1, 2016
March 21, 2017
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