The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An amplifier comprising: a first transistor configured to receive a first input; a second transistor configured to receive a second input; and a plurality of impedance networks coupled between the first transistor and the second transistor, at least one impedance network of the plurality of impedance networks comprising: a first impedance path configured to be activated during single ended operation, the first impedance path including a first impedance coupled between a terminal of the first transistor and a first node, and a first switch coupled between the first node and a terminal of the second transistor; and a second impedance path configured to be activated during differential operation, the second impedance path including a second impedance coupled between the terminal of the first transistor and a second node, a second switch coupled between the second node and a third node, and a third impedance coupled between the third node and the terminal of the second transistor.
2. The amplifier of claim 1 , wherein the first input is greater than the second input during the single ended operation.
3. The amplifier of claim 1 , wherein the first input and the second input are differential signals during the differential operation.
4. The amplifier of claim 1 , wherein the first transistor is an NPN transistor whose base terminal is configured to receive the first input, whose first terminal is an emitter terminal that is coupled to the plurality of impedance networks and whose collector terminal is coupled to a power supply through a first load resistor.
5. The amplifier of claim 4 , further comprising a first biasing current source coupled between the emitter terminal of the first transistor and a ground terminal.
6. The amplifier of claim 1 , further comprising: a first output node coupled between the first load resistor and the collector terminal of the first transistor, wherein a first output is generated at the first output node; and a second output node coupled between the second load resistor and the collector terminal of the second transistor, wherein a second output is generated at the second output node.
7. The amplifier of claim 1 , wherein during the single ended operation, the first switch is activated and the second switch is inactivated such that a voltage swing across the first switch is less than a voltage swing across the second switch.
8. The amplifier of claim 1 , wherein during the single ended operation, each of the first switch and the second switch is inactivated such that a voltage swing across both the first switch and the second switch is equal.
9. The amplifier of claim 1 , wherein during the differential operation, the first switch is inactivated and the second switch is activated such that a voltage swing across the second switch is less than a voltage swing across the first switch.
10. The amplifier of claim 1 , wherein during the differential operation, each of the first switch and the second switch is inactivated such that a voltage swing across both the first switch and the second switch is equal.
11. An amplifier comprising: a first transistor configured to receive a first input; a second transistor configured to receive a second input; and a plurality of impedance networks coupled between the first transistor and the second transistor, at least one impedance network of the plurality of impedance networks comprising: a first impedance path configured to be activated during single ended operation; and a second impedance path configured to be activated during differential operation, wherein the second transistor is an NPN transistor whose base terminal is configured to receive the second input, whose emitter terminal is coupled to the plurality of impedance networks and whose collector terminal is coupled to a power supply through a second load resistor.
12. The amplifier of claim 11 , further comprising a second biasing current source coupled between the emitter terminal of the second transistor and the ground terminal.
13. A method comprising: providing a first input and a second input to an amplifier, the amplifier including an impedance network; activating a first impedance path in the impedance network during single ended operation, the first impedance path including a first switch; and activating a second impedance path in the impedance network during differential operation, the second impedance path including a second switch, wherein during the single ended operation the first switch is activated and the second switch is inactivated such that a voltage swing across the first switch is less than a voltage swing across the second switch.
14. The method of claim 13 further comprising configuring the first input to be greater than the second input during the single ended operation, and configuring the first input and the second input as differential signals during the differential operation.
15. The method of claim 13 further comprising inactivating the first switch and the second switch during the single ended operation and during the differential operation such that a voltage swing across both the first switch and the second switch is equal.
16. A receiver comprising: a receive antenna configured to receive a signal and configured to generate a first input and a second input; an amplifier coupled to the receive antenna, the amplifier comprising: a first transistor configured to receive the first input; a second transistor configured to receive the second input; and a plurality of impedance networks coupled between the first transistor and the second transistor, at least one impedance network of the plurality of impedance networks comprising: a first impedance path configured to be activated during single ended operation, the first impedance path including a first impedance coupled between a terminal of the first transistor and a first node, and a first switch coupled between the first node and a terminal of the second transistor; and a second impedance path configured to be activated during differential operation, the second impedance path including a second impedance coupled between the terminal of the first transistor and a second node, a second switch coupled between the second node and a third node, and a third impedance coupled between the third node and the terminal of the second transistor; an IF filter coupled to the amplifier and configured to generate a filtered non-zero IF signal from a signal received from the amplifier; an analog to digital converter (ADC) coupled to the IF filter and configured to sample the filtered non-zero IF signal to generate a valid data; and a processor coupled to the ADC and configured to process the valid data.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 1, 2016
March 21, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.