Patentable/Patents/US-9607716
US-9607716

Detecting defective connections in stacked memory devices

PublishedMarch 28, 2017
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.

Patent Claims
4 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A stacked memory device comprising: a plurality of memory chips each having a plurality of memory locations, a plurality of bit lines and a plurality of word lines; and, a logic chip having electrical connections to, and located beneath, each of the plurality of memory chips, and designed to: write a write data value into a location of the plurality of memory locations in a memory chip of the plurality of memory chips; read a read data value from the location in the memory chip; detect a bit error in the read data value; record a bit number corresponding to a detected bit error; and, replace a defective connection between at least one of the plurality of memory chips and the logic chip, with a spare connection.

2

2. The stacked memory device of claim 1 , wherein the electrical connections are through-silicon vias (TSVs).

3

3. The stacked memory device of claim 1 , wherein the logic chip is a member of a group consisting of: a processor chip, a memory controller chip and a memory buffer chip.

4

4. The stacked memory device of claim 1 , wherein a multiplexer is configured to replace the defective connection with a spare connection.

Classification Codes (CPC)

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Patent Metadata

Filing Date

April 9, 2014

Publication Date

March 28, 2017

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Cite as: Patentable. “Detecting defective connections in stacked memory devices” (US-9607716). https://patentable.app/patents/US-9607716

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