Semiconductor device manufacturing methods and methods of forming insulating material layers

1. A method of forming a semiconductor device, the method comprising: forming a fin structure protruding from a substrate; depositing a dielectric buffer layer on the fin structure using a first plasma power level; depositing a gate dielectric layer over the dielectric buffer layer, wherein the gate dielectric layer has an exposed top surface, and is deposited using a second plasma power level different from the first plasma power level; and annealing the fin structure while the gate dielectric layer top surface remains exposed to improve the interface quality of the gate dielectric layer.

2. The method of claim 1 , wherein depositing the dielectric buffer layer comprises using a low temperature atomic layer deposition (ALD) process without plasma.

3. The method of claim 1 , wherein depositing the dielectric buffer layer comprises an atomic layer deposition (ALD) process with a plasma power of less than about 50 W.

4. The method of claim 1 , wherein depositing the gate dielectric layer comprises an atomic layer deposition process with a plasma power of greater than about 100 W.

5. The method of claim 1 , wherein the process for depositing the dielectric buffer layer consumes less material of the fin structure than does the process for depositing the gate dielectric layer.

6. The method of claim 1 , further comprising performing a plasma treatment after forming the dielectric buffer layer and before forming the gate dielectric layer.

7. The method of claim 1 , wherein the step of annealing the fin structure forms another dielectric layer on the gate dielectric layer.

8. The method of claim 7 , wherein the dielectric buffer layer and the gate dielectric layer comprise silicon oxide and the another dielectric layer comprises silicon oxynitride.

9. A method of manufacturing a semiconductor device, the method comprising: forming a fin disposed on a surface of a substrate; forming a first gate dielectric sub-layer on the fin using a first atomic layer deposition (ALD) process at a first plasma level; forming a second gate dielectric sub-layer on the first gate dielectric sub-layer using a second ALD process at a second plasma level; and performing an anneal process on the first and second gate dielectric sub-layers.

10. The method of claim 9 , wherein the first plasma level is no plasma.

11. The method of claim 9 , wherein the first plasma level is below about 50 W.

12. The method of claim 9 , wherein the process for depositing the first gate dielectric sub-lay consumes less material of the fin than does the process for depositing the second gate dielectric sub-layer.

13. The method of claim 9 , further comprising forming a thermal oxide layer on the fin before forming the first gate dielectric sub-layer.

14. The method of claim 9 , wherein the second plasma level is above about 100 W.

15. The method of claim 9 , further comprising forming a high k dielectric material over the fin, after the anneal process.

16. The method of claim 9 , wherein the anneal process forms a silicon oxynitride layer on the second gate dielectric sub-layer.

17. A method of forming a semiconductor device, the method comprising: providing a workpiece comprising a semiconductor material; forming a first sub-layer of a gate dielectric layer over the workpiece using a first deposition process that is configured to consume a lesser amount of the semiconductor material relative to a second deposition process; forming a second sub-layer of the gate dielectric layer over the first sub-layer of the gate dielectric layer using the second deposition process; and annealing the workpiece after the forming the second sub-layer of the gate dielectric layer and while the second sub-layer of the gate dielectric layer is free of overlying.

18. The method of claim 17 , wherein the first deposition process comprises a plasma power level of about 50 Watts or less, and wherein the second deposition process a plasma power level of about 100 Watts or greater.

19. The method of claim 17 , wherein the step of annealing the workpiece improves a film quality at an interface of the gate dielectric layer.

20. The method of claim 17 , wherein the step of forming a first sub-layer of a gate dielectric layer comprises an atomic layer deposition process at a first plasma level and the step of forming a second sub-layer of the gate dielectric layer comprises an atomic layer deposition process at a second plasma level higher than the first plasma level.