Performance analysis for an electronic system includes determining, using a processor, data traffic patterns stored within a core library of an electronic design automation system, wherein the data traffic patterns are part of cores stored within the core library. The determined data traffic patterns are displayed using a display as modeling options. A user input selecting a displayed data traffic pattern is received; and the selected data traffic pattern is executed as part of modeling the electronic system.
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1. A method, comprising: determining, using a processor of a data processing system, data traffic patterns stored within a core library of an electronic design automation system; wherein the data traffic patterns are specified by cores stored within the core library; displaying, using a display device, the determined data traffic patterns as modeling options; receiving a user input selecting a displayed data traffic pattern associated with a selected core; and executing the selected data traffic pattern as part of modeling an electronic system to generate data traffic that mimics operation of the selected core by programming an emulation circuit implemented within an integrated circuit with the selected data traffic pattern and executing the selected data traffic pattern to generate the data traffic between the emulation circuit and a processor system of the integrated circuit.
A method for analyzing electronic system performance involves a computer analyzing data traffic patterns from a core library within an electronic design automation (EDA) system. These traffic patterns are defined by reusable cores in the library. The system displays these patterns as modeling options to the user. When a user selects a traffic pattern associated with a specific core, the system executes this pattern to model the electronic system's behavior. This is achieved by programming an emulation circuit (on an integrated circuit) with the chosen traffic pattern. This emulation circuit then generates data traffic, mimicking the operation of the selected core, interacting with the integrated circuit's processor system.
2. The method of claim 1 , wherein the emulation circuit executing the selected data traffic pattern emulates an off-chip interface of the electronic system.
The method described above, where data traffic patterns from a core library are used to model an electronic system, involves the emulation circuit specifically mimicking an off-chip interface of the electronic system when executing the selected data traffic pattern. This means the emulation circuit simulates how the selected core would communicate with external components outside the main integrated circuit.
3. The method of claim 2 , further comprising: responsive to a user input, replacing the emulation circuit within the integrated circuit with an implementation of the selected core.
The method described above, where data traffic patterns from a core library are used to model an electronic system using an emulation circuit, further includes replacing the emulation circuit on the integrated circuit with an actual implementation of the selected core in response to a user command. This allows transitioning from a simulation to a real hardware implementation of the core within the system.
4. The method of claim 3 , wherein replacing the emulation circuit within the integrated circuit comprises: generating a configuration bitstream wherein the selected core replaces the emulation circuit and providing the configuration bitstream to the integrated circuit for implementation therein.
The method described above, where data traffic patterns from a core library are used to model an electronic system, and the emulation circuit is replaced, the act of replacing the emulation circuit on the integrated circuit involves generating a configuration bitstream. This bitstream contains the design specifying that the selected core now occupies the space of the emulation circuit. This bitstream is then provided to the integrated circuit, effectively reconfiguring it to implement the actual core instead of the emulator.
5. The method of claim 1 , wherein executing the selected data traffic pattern as part of modeling an electronic system comprises: simulating the electronic system using the data processing system by using a software model to execute the selected data traffic pattern to generate the data traffic.
The method described above, where data traffic patterns from a core library are used to model an electronic system, includes the step of simulating the electronic system using software. This simulation uses a software model to execute the selected data traffic pattern, creating realistic data traffic that represents the core's behavior within the system. This allows for software-based analysis and validation of the electronic system's performance.
6. The method of claim 1 , further comprising: determining an item of traffic scenario data associated with the selected data traffic pattern; wherein the item of traffic scenario data is at least one of an item of runtime configuration data or a processor program; and executing the item of traffic scenario data using the processor system of the integrated circuit during modeling of the electronic system.
The method described above, where data traffic patterns from a core library are used to model an electronic system, further involves determining "traffic scenario data" linked to the chosen data traffic pattern. This traffic scenario data includes runtime configuration data or a processor program relevant to the selected core's operation. This configuration or program is then executed by the integrated circuit's processor system during the electronic system modeling process, adding more context to the simulation.
7. A system, comprising: a host data processing system comprising a memory storing program code, a display device, and a processor coupled to the memory and the display device; wherein the processor, upon executing the program code, is programmed to initiate executable operations comprising: determining data traffic patterns stored within a core library of an electronic design automation system; wherein the data traffic patterns are specified by cores stored within the core library; displaying on the display device the determined data traffic patterns as modeling options; receiving a user input selecting a displayed data traffic pattern associated with a selected core; and executing the selected data traffic pattern as part of modeling an electronic system to generate data traffic that mimics operation of the selected core by programming an emulation circuit implemented within an integrated circuit with the selected data traffic pattern and executing the selected data traffic pattern to generate the data traffic between the emulation circuit and a processor system of the integrated circuit.
A system for analyzing electronic system performance has a host computer including memory for program code, a display, and a processor connected to both. The processor runs code to: analyze data traffic patterns from a core library within an electronic design automation (EDA) system, where these traffic patterns are defined by reusable cores; display these patterns as modeling options; receive user selection of a pattern linked to a specific core; and execute this pattern to model the electronic system. The system programs an emulation circuit (on an integrated circuit) with the traffic pattern. The emulation circuit generates traffic, mimicking the selected core's operation, interacting with the integrated circuit's processor system.
8. The system of claim 7 , wherein the emulation circuit executing the selected data traffic pattern emulates an off-chip interface of the electronic system.
The system described above, where data traffic patterns from a core library are used to model an electronic system, where the emulation circuit specifically mimics an off-chip interface of the electronic system when executing the selected data traffic pattern. This means the emulation circuit simulates how the selected core would communicate with external components outside the main integrated circuit.
9. The system of claim 7 , wherein the processor of the host data processing system further initiates executable operations comprising: responsive to a user input, replacing the emulation circuit within the integrated circuit with an implementation of the selected core.
The system described above, where data traffic patterns from a core library are used to model an electronic system using an emulation circuit, and the host computer’s processor further initiates operations to replace the emulation circuit on the integrated circuit with an actual implementation of the selected core, based on user input. This allows transitioning from simulation to a real hardware implementation of the core within the system.
10. The system of claim 8 , wherein replacing the emulation circuit within the integrated circuit comprises: generating a configuration bitstream specifying the emulation system wherein the core replaces the emulation circuit and providing the configuration bitstream to the integrated circuit for implementation therein.
The system described above, where data traffic patterns from a core library are used to model an electronic system, and the emulation circuit is replaced, and replacing the emulation circuit involves generating a configuration bitstream. This bitstream instructs the system to implement the selected core in place of the emulation circuit. This bitstream is provided to the integrated circuit, reconfiguring it to implement the core instead of the emulator.
11. The system of claim 7 , wherein executing the selected data traffic pattern as part of modeling an electronic system comprises: simulating the electronic system using the host data processing system by using a software model to execute the selected data traffic pattern to generate the data traffic.
The system described above, where data traffic patterns from a core library are used to model an electronic system, where executing the selected traffic pattern means simulating the system using the host computer. A software model runs the traffic pattern, creating data traffic that represents the core's behavior. This allows software-based analysis of the electronic system's performance.
12. The system of claim 7 , wherein: the processor of the host data processing system further initiates executable operations comprising determining an item of traffic scenario data associated with the selected data traffic pattern, wherein the item of traffic scenario data is at least one of an item of runtime configuration data or a processor program; and the processor system of the integrated circuit is configured to execute the item of traffic scenario data during modeling of the electronic system.
The system described above, where data traffic patterns from a core library are used to model an electronic system, where the host computer's processor determines "traffic scenario data" for the chosen traffic pattern. This includes runtime configuration data or a processor program for the selected core. The integrated circuit's processor then runs this scenario data during system modeling, providing context to the simulation.
13. A non-transitory computer-readable medium having instructions which, when executed by a processor, perform a method comprising: determining, using the processor, data traffic patterns stored within a core library of an electronic design automation system; wherein the data traffic patterns are specified by cores stored within the core library; displaying, using a display device, the determined data traffic patterns as modeling options; receiving a user input selecting a displayed data traffic pattern associated with a selected core; and executing the selected data traffic pattern as part of modeling an electronic system to generate data traffic that mimics operation of the selected core by programming an emulation circuit implemented within an integrated circuit with the selected data traffic pattern and executing the selected data traffic pattern to generate the data traffic between the emulation circuit and a processor system of the integrated circuit.
A non-transitory computer-readable medium contains instructions. When executed by a processor, these instructions cause the processor to: analyze data traffic patterns from a core library within an electronic design automation (EDA) system, where these traffic patterns are defined by reusable cores; display these patterns as modeling options; receive user selection of a pattern linked to a specific core; and execute this pattern to model the electronic system. The instructions program an emulation circuit (on an integrated circuit) with the traffic pattern. The emulation circuit generates traffic, mimicking the selected core's operation, interacting with the integrated circuit's processor system.
14. The non-transitory computer-readable medium of claim 13 , wherein the method further comprises: responsive to a user input, replacing the emulation circuit within the integrated circuit with an implementation of the selected core.
The computer-readable medium described above, where data traffic patterns from a core library are used to model an electronic system using an emulation circuit, wherein the instructions further cause the processor to replace the emulation circuit on the integrated circuit with an actual implementation of the selected core, based on user input.
15. The non-transitory computer-readable medium of claim 14 , wherein the method further comprises: generating a configuration bitstream for the emulation system wherein the selected core replaces the emulation circuit and providing the configuration bitstream to the integrated circuit for implementation therein.
The computer-readable medium described above, where data traffic patterns from a core library are used to model an electronic system, and the emulation circuit is replaced, the instructions further cause the processor to generate a configuration bitstream. This bitstream instructs the system to implement the selected core in place of the emulation circuit.
16. The non-transitory computer-readable medium of claim 13 , wherein executing the selected data traffic pattern as part of modeling an electronic system comprises: simulating the electronic system using the processor by using a software model to execute the selected data traffic pattern to generate the data traffic.
The computer-readable medium described above, where data traffic patterns from a core library are used to model an electronic system, wherein executing the selected traffic pattern means simulating the system using the processor. A software model runs the traffic pattern, creating data traffic that represents the core's behavior.
17. The non-transitory computer-readable medium of claim 13 , wherein the method further comprises: determining an item of traffic scenario data associated with the selected data traffic pattern; wherein the item of traffic scenario data is at least one of an item of runtime configuration data or a processor program; and executing the item of traffic scenario data using the processor system of the integrated circuit during modeling of the electronic system.
The computer-readable medium described above, where data traffic patterns from a core library are used to model an electronic system, wherein the instructions further cause the processor to determine "traffic scenario data" for the chosen traffic pattern. This includes runtime configuration data or a processor program for the selected core. The integrated circuit's processor then runs this scenario data during system modeling.
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May 16, 2014
March 28, 2017
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