Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.
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1. A method, comprising: applying a first voltage to a first conductive line that is in electronic communication with a ferroelectric memory cell that is in electronic communication with a selection component, wherein the first voltage is applied during an access operation; applying a second voltage to a second conductive line that is in electronic communication with the selection component, wherein the second voltage is applied during the access operation, and wherein a voltage across the ferroelectric memory cell and the selection component during the access operation comprises a difference between the first voltage and the second voltage; and applying a third voltage to the first conductive line during a discharge operation following the access operation, wherein the third voltage has an amplitude that is based at least in part on a threshold voltage of the selection component.
A method for writing to a ferroelectric memory cell involves applying a first voltage to a first conductive line connected to the memory cell and a selection component during a write or read access operation. A second voltage is applied to a second conductive line connected to the selection component during the same access operation, creating a voltage difference across the memory cell and selection component. Following the access, a third voltage is applied to the first conductive line to discharge the cell. The magnitude of this third voltage is determined based on the threshold voltage of the selection component, preventing unwanted state changes in adjacent cells.
2. The method of claim 1 , wherein the second voltage and the third voltage have an opposite polarity from the first voltage.
In the ferroelectric memory writing method described previously, the second voltage applied to the second conductive line during the access operation and the third voltage applied to the first conductive line during the discharge operation have opposite polarity compared to the first voltage applied during the access operation. This polarity reversal helps to effectively discharge the memory cell and prevent disturb errors in neighboring cells.
3. The method of claim 2 , further comprising: applying a fourth voltage to the second conductive line during the discharge operation, wherein the fourth voltage has an opposite polarity from the second voltage and an amplitude that is based at least in part on the threshold voltage of the selection component.
Expanding on the ferroelectric memory writing method where voltages are applied to conductive lines to access and discharge memory cells, a fourth voltage is applied to the second conductive line during the discharge operation. This fourth voltage has an opposite polarity from the second voltage and its amplitude is based on the threshold voltage of the selection component. This controlled discharge helps prevent unintended writing to unselected memory cells.
4. The method of claim 3 , wherein applying the fourth voltage comprises: applying the fourth voltage after applying the third voltage.
In the ferroelectric memory writing method where a fourth voltage is applied to the second conductive line during the discharge operation, the fourth voltage is applied after the third voltage is applied to the first conductive line. This sequential application ensures controlled discharging and minimizes disturbance to adjacent memory cells after an access operation.
5. The method of claim 3 , wherein applying the fourth voltage comprises: applying the fourth voltage simultaneously with the third voltage, wherein a voltage across the ferroelectric memory cell and the selection component during the discharge operation comprises a difference between the third voltage and the fourth voltage.
Alternatively, the ferroelectric memory cell writing method applies the fourth voltage to the second conductive line simultaneously with applying the third voltage to the first conductive line during the discharge operation. In this case, the voltage across the ferroelectric memory cell and the selection component during the discharge operation is the difference between the third and fourth voltages. Simultaneous application allows for a more precise control of the discharge process.
6. The method of claim 3 , wherein the amplitude of the fourth voltage is less than or equal to an amplitude of the second voltage.
In the ferroelectric memory cell writing method, the amplitude of the fourth voltage applied to the second conductive line during the discharge operation is less than or equal to the amplitude of the second voltage applied during the access operation. Restricting the fourth voltage amplitude ensures that the discharge voltage remains within safe operating limits and prevents accidental writing to the memory cell.
7. The method of claim 3 , wherein the amplitude of the fourth voltage is equal to the amplitude of the third voltage.
In the ferroelectric memory cell writing method, the amplitude of the fourth voltage applied to the second conductive line during the discharge operation is equal to the amplitude of the third voltage applied to the first conductive line during the same discharge operation. Equal amplitudes simplify the voltage control circuitry and provide a balanced discharge condition.
8. The method of claim 1 , wherein the first voltage is greater than a relative voltage and the second voltage and the third voltage are less than the relative voltage.
In the ferroelectric memory cell writing method, the first voltage applied to the first conductive line during the access operation is greater than a relative voltage, and both the second voltage applied to the second conductive line during the access operation and the third voltage applied to the first conductive line during the discharge operation are less than the relative voltage. This creates a voltage difference necessary for the write/read operation and ensures effective cell discharging.
9. The method of claim 1 , wherein a voltage across the ferroelectric memory cell and the selection component during the discharge operation comprises the third voltage.
In the ferroelectric memory cell writing method, the voltage across the ferroelectric memory cell and the selection component during the discharge operation is simply the third voltage applied to the first conductive line. This simplified discharge approach omits applying a fourth voltage and relies solely on the third voltage to reduce the voltage across the memory cell.
10. The method of claim 1 , wherein the selection component comprises an electrically non-linear component.
In the ferroelectric memory cell writing method, the selection component used is an electrically non-linear component. Using a non-linear component such as a diode or transistor allows for selective access to individual memory cells within a larger array.
11. The method of claim 1 , wherein the voltage across the ferroelectric memory cell and the selection component during the access operation is greater than the threshold voltage of the selection component.
In the ferroelectric memory cell writing method, the voltage across the ferroelectric memory cell and the selection component during the access operation is greater than the threshold voltage of the selection component. This ensures that the selection component is turned on, allowing current to flow through the memory cell during the write or read process.
12. The method of claim 1 , wherein a voltage across the ferroelectric memory cell and the selection component during the discharge operation is less than the threshold voltage of the selection component.
In the ferroelectric memory cell writing method, the voltage across the ferroelectric memory cell and the selection component during the discharge operation is less than the threshold voltage of the selection component. This ensures the selection component is turned off, preventing unintended writing to other cells due to the discharge voltage.
13. The method of claim 1 , wherein an amplitude of the first voltage is equal to an amplitude of the second voltage.
In the ferroelectric memory cell writing method, the amplitude of the first voltage applied to the first conductive line during the access operation is equal to the amplitude of the second voltage applied to the second conductive line during the same access operation. This equal amplitude simplifies the voltage driving circuitry but relies on opposite polarities to generate the necessary voltage differential.
14. The method of claim 1 , wherein the first voltage is applied for a first time period and the third voltage is applied for a second time period that is less than or equal to the first time period.
In the ferroelectric memory cell writing method, the first voltage applied during the access operation is applied for a first time period, and the third voltage applied during the discharge operation is applied for a second time period that is less than or equal to the first time period. This ensures the memory cell is fully accessed before the discharge process begins, and the discharge is applied for a sufficient amount of time to neutralize the voltage.
15. A method, comprising: applying an access voltage to a ferroelectric memory cell that is in electronic communication with a selection component during an access operation, wherein an amplitude of the access voltage is greater than a threshold voltage of the selection component; and applying a first discharge voltage to the ferroelectric memory cell following the access operation, wherein a polarity of the first discharge voltage is opposite to a polarity of the access voltage, and wherein an amplitude of the first discharge voltage is less than the threshold voltage of the selection component.
A method for writing to a ferroelectric memory cell with a selection component involves applying an access voltage during an access operation. The access voltage is greater than the selection component's threshold voltage. After the access, a first discharge voltage, with opposite polarity to the access voltage and an amplitude less than the threshold voltage of the selection component, is applied to the ferroelectric memory cell. This helps prevent disturbance of unselected memory cells.
16. The method of claim 15 , further comprising: applying a second discharge voltage to the ferroelectric memory cell following the first discharge voltage, wherein a polarity of the second discharge voltage is opposite to the polarity of the access voltage, and wherein an amplitude of the second discharge voltage is less than the threshold voltage of the selection component.
Expanding upon the ferroelectric memory cell writing method of applying access and discharge voltages, a second discharge voltage is applied following the first discharge voltage. The second discharge voltage has the same polarity as the first discharge voltage, opposite that of the access voltage. The amplitude of the second discharge voltage is also less than the threshold voltage of the selection component to further reduce the likelihood of unwanted writes to neighboring cells.
17. The method of claim 15 , wherein the amplitude of the first discharge voltage is less than or equal to one-half of the amplitude of the access voltage.
In the ferroelectric memory cell writing method utilizing access and discharge voltages, the amplitude of the first discharge voltage is less than or equal to one-half of the amplitude of the access voltage. This limits the magnitude of the discharge, preventing accidental state changes in targeted or untargeted memory cells.
18. The method of claim 15 , wherein the selection component comprises a metal-semiconductor switch, a metal-semiconductor-metal switch, or a chalcogenide material.
In the ferroelectric memory cell writing method, the selection component comprises a metal-semiconductor switch, a metal-semiconductor-metal switch, or a chalcogenide material. These selection components provide the necessary non-linear behavior for selective memory cell access.
19. A method, comprising: performing a first access operation for a first ferroelectric memory cell of a memory array comprising a plurality of ferroelectric memory cells; starting a timer based at least in part on performing the first access operation; and performing a second access operation for a second ferroelectric memory cell of the memory array based at least in part on the timer exceeding a threshold, wherein the threshold is based at least in part on a discharge rate of the first ferroelectric memory cell.
To prevent disturb errors in a memory array with multiple ferroelectric memory cells, this method involves performing an access operation on a first memory cell and starting a timer. A second access operation on a second memory cell is delayed until the timer exceeds a threshold. The threshold is based on the discharge rate of the first memory cell, ensuring it has sufficient time to settle before another cell is accessed, thus mitigating unwanted voltage leaks.
20. The method of claim 19 , further comprising: resetting the timer based at least in part on performing the second access operation.
Extending the memory array access method that uses a timer to prevent disturb errors, the timer is reset after performing the second access operation. This resetting action begins the timing cycle anew for the next memory cell access.
21. The method of claim 19 , wherein: the first ferroelectric memory cell is in electronic communication with the second ferroelectric memory cell of the memory array; a charge of the second ferroelectric memory cell is based at least in part on the first access operation for the first ferroelectric memory cell; and the threshold is based at least in part on a time to discharge the second ferroelectric memory cell.
Further refining the memory array access method with a timer, the first and second memory cells are in electronic communication. The charge of the second memory cell is influenced by the access operation of the first memory cell. The timer threshold is based on the time it takes to discharge the second memory cell after the first cell is accessed.
22. The method of claim 19 , further comprising: accessing a third ferroelectric memory cell before the timer exceeds the threshold, wherein the third ferroelectric memory cell is isolated from the first ferroelectric memory cell.
In the ferroelectric memory array management method using a timer to avoid disturb errors, access to a third memory cell can occur before the timer threshold is reached, provided the third memory cell is electrically isolated from the first memory cell. This allows accessing independent memory cells without waiting for the discharge time of other cells.
23. The method of claim 19 , wherein the timer comprises a count-down timer, and wherein performing the second access operation comprises: performing the second access operation based at least in part on an expiration of the timer.
In the ferroelectric memory array management method that uses a timer to avoid disturb errors, the timer is a count-down timer. The second access operation is performed when this timer expires. Thus, the second access occurs only after the predetermined discharge delay has elapsed.
24. A method, comprising: applying during an access operation an access voltage to a ferroelectric memory cell that is in electronic communication with a selection component, wherein an amplitude of the access voltage is greater than a threshold voltage of the selection component; incrementing a counter based at least in part on applying the access voltage; and applying a discharge voltage to the ferroelectric memory cell based at least in part on the counter exceeding a threshold, wherein a polarity of the discharge voltage is opposite to a polarity of the access voltage, and wherein an amplitude of the discharge voltage is less than the threshold voltage of the selection component.
A method for writing to a ferroelectric memory cell with a selection component applies an access voltage higher than the selection component's threshold during writing. A counter increments each time the access voltage is applied. A discharge voltage, with opposite polarity to the access voltage and an amplitude lower than the selection component's threshold voltage, is applied only after the counter exceeds a threshold. This manages write endurance and disturb issues by controlling the frequency of discharge operations.
25. The method of claim 24 , wherein a memory array comprises a plurality of memory cells, the plurality of memory cells comprising the ferroelectric memory cell, and wherein applying the discharge voltage to the ferroelectric memory cell comprises: applying the discharge voltage to the plurality of memory cells of the memory array.
In the memory cell writing method that uses a counter to trigger discharge, when a memory array contains the ferroelectric memory cell, applying the discharge voltage involves applying the discharge voltage to all the memory cells in the array. This ensures a uniform discharge process across all cells in the memory array.
26. The method of claim 24 , wherein the threshold is based at least in part on a rate of access attempts of the ferroelectric memory cell.
In the ferroelectric memory cell writing method where a counter triggers a discharge, the threshold for the counter is based on the rate of access attempts to the memory cell. Frequent access attempts will result in a faster incrementing of the counter, leading to more frequent discharge operations.
27. The method of claim 24 , wherein the ferroelectric memory cell and the selection component are in electronic communication with a first conductive line and a second conductive line, and wherein applying the access voltage to the ferroelectric memory cell comprises: applying a first voltage to the first conductive line and applying a second voltage to the second conductive line, wherein the access voltage comprises a voltage difference between the first voltage and the second voltage.
In the ferroelectric memory cell writing method, where a counter is used to trigger a discharge, the ferroelectric memory cell and its selection component are connected to first and second conductive lines. Applying the access voltage involves applying a first voltage to the first line and a second voltage to the second line, where the access voltage is the voltage difference between these two.
28. The method of claim 27 , wherein applying the discharge voltage to the ferroelectric memory cell comprises: applying a third voltage to the first conductive line, wherein the third voltage has an opposite polarity from the first voltage, and wherein a voltage across the ferroelectric memory cell and the selection component comprises the third voltage.
In the ferroelectric memory cell writing method involving conductive lines and a counter-triggered discharge, the discharge voltage is applied by applying a third voltage to the first conductive line. The third voltage has the opposite polarity to the first voltage, and the voltage across the memory cell and selection component is equal to this third voltage.
29. The method of claim 28 , wherein applying the discharge voltage to the ferroelectric memory cell comprises: applying a fourth voltage to the second conductive line after the third voltage is applied to the first conductive line, wherein the fourth voltage has an opposite polarity from the second voltage, and wherein a voltage across the ferroelectric memory cell and the selection component comprises the fourth voltage.
In the memory cell writing method involving conductive lines and a counter-triggered discharge, after applying a third voltage to the first conductive line for discharge, a fourth voltage is applied to the second conductive line. The fourth voltage has the opposite polarity to the second voltage, and the voltage across the memory cell and selection component is equal to the fourth voltage.
30. The method of claim 28 , wherein the second voltage and the third voltage have an opposite polarity from the first voltage, and wherein applying the discharge voltage to the ferroelectric memory cell comprises: applying a fourth voltage to the second conductive line simultaneously with the third voltage, wherein the fourth voltage has an opposite polarity from the second voltage, and wherein a voltage across the ferroelectric memory cell and the selection component comprises a difference between the fourth voltage and the third voltage.
In the ferroelectric memory cell writing method using conductive lines and a counter, the second and third voltages have opposite polarity to the first. The discharge is applied by simultaneously applying a third voltage to the first conductive line and a fourth voltage to the second conductive line. The fourth voltage also has opposite polarity to the second voltage. The voltage across the memory cell and the selection component becomes the difference between the fourth and third voltages.
31. An apparatus, comprising: a ferroelectric memory cell and a selection component in electronic communication with and positioned between a first conductive line and a second conductive line; and a controller in electronic communication with the first conductive line and the second conductive line, wherein the controller is operable to: apply a first voltage to the first conductive line during an access operation; apply a second voltage to the second conductive line during the access operation, wherein a voltage across the ferroelectric memory cell and the selection component during the access operation comprises a difference between the first voltage and the second voltage; and apply a third voltage to the first conductive line during a discharge operation following the access operation, wherein the third voltage has an amplitude that is based at least in part on a threshold voltage of the selection component.
An apparatus for ferroelectric memory includes a ferroelectric memory cell and a selection component positioned between first and second conductive lines. A controller applies a first voltage to the first conductive line during an access operation and a second voltage to the second conductive line. The voltage across the memory cell and selection component is the difference between these voltages. After access, the controller applies a third voltage to the first conductive line to discharge the cell. The third voltage's magnitude depends on the selection component's threshold voltage.
32. The apparatus of claim 31 , wherein the controller is operable to: apply a fourth voltage to the second conductive line during the discharge operation, wherein the fourth voltage has an opposite polarity from the second voltage and has an amplitude based at least in part on the threshold voltage of the selection component.
The ferroelectric memory apparatus described includes a controller that also applies a fourth voltage to the second conductive line during the discharge operation. This fourth voltage has the opposite polarity from the second voltage and its amplitude is determined based on the threshold voltage of the selection component.
33. The apparatus of claim 31 , further comprising: a pillar in contact with the first conductive line and the second conductive line, wherein the pillar comprises a first electrode, the selection component, and the ferroelectric memory cell, wherein the ferroelectric memory cell comprises a second electrode, a ferroelectric memory element, and a third electrode.
The ferroelectric memory apparatus includes a pillar in contact with both conductive lines. This pillar contains a first electrode, the selection component, and the ferroelectric memory cell. The memory cell comprises a second electrode, a ferroelectric memory element, and a third electrode. This describes the physical arrangement of the memory cell components.
34. The apparatus of claim 31 , further comprising: a counter, wherein the controller is operable to: increment the counter based at least in part on applying the first voltage or the second voltage during the access operation.
In the ferroelectric memory apparatus, a counter is used. The controller increments this counter each time the first voltage or the second voltage is applied during the access operation. This facilitates tracking the number of access events.
35. The apparatus of claim 31 , further comprising: a voltage regulator, wherein the amplitude of the third voltage is based at least in part on an output of the voltage regulator, and wherein the controller is operable to: apply the third voltage to the first conductive line during the discharge operation, wherein the amplitude of the third voltage is less than an amplitude of the first voltage.
The ferroelectric memory apparatus incorporates a voltage regulator. The amplitude of the third voltage, used for discharge, is based on the output of this voltage regulator. The controller applies the third voltage to the first conductive line during the discharge operation, with the amplitude of the third voltage being less than the amplitude of the first voltage. This ensures that the discharge voltage remains within a safe operating range.
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June 29, 2016
April 4, 2017
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