A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A device comprising: silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate; a silicon dioxide (SiO 2 ) liner over the Si fins in the nFET region; a dielectric layer disposed between a lower portion of the Si fins, leaving an exposed upper portion of the Si fins; and a siliconborocarbonitride (SiBCN) liner disposed between the SiO 2 liner and the dielectric layer, and directly on a bottom surface of the dielectric layer.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region only. A dielectric layer sits between the lower parts of the fins, exposing the upper parts. A siliconborocarbonitride (SiBCN) liner is positioned between the SiO2 liner and the dielectric layer and also directly on the bottom surface of the dielectric layer.
2. The device according to claim 1 , wherein the exposed upper portion of the Si fins in the pFET region comprises silicon germanium (SiGe).
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region only. A dielectric layer sits between the lower parts of the fins, exposing the upper parts. A siliconborocarbonitride (SiBCN) liner is positioned between the SiO2 liner and the dielectric layer and also directly on the bottom surface of the dielectric layer. The upper part of the silicon fins in the pFET region is made of silicon germanium (SiGe).
3. The device according to claim 2 , wherein the SiO 2 liner in the nFET region is disposed between the SiBCN liner and the Si fins.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region only. A dielectric layer sits between the lower parts of the fins, exposing the upper parts. A siliconborocarbonitride (SiBCN) liner is positioned between the SiO2 liner and the dielectric layer and also directly on the bottom surface of the dielectric layer. The upper part of the silicon fins in the pFET region is made of silicon germanium (SiGe). The SiO2 liner in the nFET region is located between the SiBCN liner and the silicon fins.
4. The device according to claim 3 , wherein the SiO 2 liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region only. A dielectric layer sits between the lower parts of the fins, exposing the upper parts. A siliconborocarbonitride (SiBCN) liner is positioned between the SiO2 liner and the dielectric layer and also directly on the bottom surface of the dielectric layer. The upper part of the silicon fins in the pFET region is made of silicon germanium (SiGe). The SiO2 liner in the nFET region is located between the SiBCN liner and the silicon fins. The SiO2 liner is 1 nanometer thick on either side of the silicon fins.
5. The device according to claim 1 , further comprising: a SiN liner disposed on the Si fins in the pFET region between the SiBCN liner and the Si fins.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region only. A dielectric layer sits between the lower parts of the fins, exposing the upper parts. A siliconborocarbonitride (SiBCN) liner is positioned between the SiO2 liner and the dielectric layer and also directly on the bottom surface of the dielectric layer. A silicon nitride (SiN) liner is present on the silicon fins in the pFET region between the SiBCN liner and the silicon fins.
6. The device according to claim 1 , wherein the nFET channel region is doped with boron (B).
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region only. A dielectric layer sits between the lower parts of the fins, exposing the upper parts. A siliconborocarbonitride (SiBCN) liner is positioned between the SiO2 liner and the dielectric layer and also directly on the bottom surface of the dielectric layer. The nFET channel region is doped with boron.
7. The device according to claim 1 , wherein the dielectric layer comprises SiO 2 .
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region only. A dielectric layer sits between the lower parts of the fins, exposing the upper parts. A siliconborocarbonitride (SiBCN) liner is positioned between the SiO2 liner and the dielectric layer and also directly on the bottom surface of the dielectric layer. The dielectric layer is made of SiO2.
8. A device comprising: silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; an oxide liner formed over the Si fins in the nFET region; a silicon dioxide (SiO 2 ) dielectric layer disposed between the Si fins, leaving an exposed upper portion of the Si fins; and a diffusion barrier liner disposed between the oxide liner and the SiO 2 dielectric layer, and directly on a bottom surface of the SiO 2 dielectric layer.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. Each fin has a silicon nitride (SiN) cap. An oxide liner covers the silicon fins in the nFET region. A silicon dioxide (SiO2) dielectric layer fills the space between the silicon fins, leaving the upper portions exposed. A diffusion barrier liner is placed between the oxide liner and the SiO2 dielectric layer, and is also directly on the bottom surface of the SiO2 dielectric layer.
9. The device according to claim 8 , wherein the diffusion barrier liner comprises siliconborocarbonitride (SiBCN).
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. Each fin has a silicon nitride (SiN) cap. An oxide liner covers the silicon fins in the nFET region. A silicon dioxide (SiO2) dielectric layer fills the space between the silicon fins, leaving the upper portions exposed. A diffusion barrier liner is placed between the oxide liner and the SiO2 dielectric layer, and is also directly on the bottom surface of the SiO2 dielectric layer. The diffusion barrier liner is made of siliconborocarbonitride (SiBCN).
10. The device according to claim 8 , wherein the SiO 2 dielectric layer is densified by way of annealing.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. Each fin has a silicon nitride (SiN) cap. An oxide liner covers the silicon fins in the nFET region. A silicon dioxide (SiO2) dielectric layer fills the space between the silicon fins, leaving the upper portions exposed. A diffusion barrier liner is placed between the oxide liner and the SiO2 dielectric layer, and is also directly on the bottom surface of the SiO2 dielectric layer. The SiO2 dielectric layer is densified through annealing.
11. The device according to claim 8 , wherein an upper portion of the Si fins in the pFET region comprise silicon germanium (SiGe).
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. Each fin has a silicon nitride (SiN) cap. An oxide liner covers the silicon fins in the nFET region. A silicon dioxide (SiO2) dielectric layer fills the space between the silicon fins, leaving the upper portions exposed. A diffusion barrier liner is placed between the oxide liner and the SiO2 dielectric layer, and is also directly on the bottom surface of the SiO2 dielectric layer. The upper part of the silicon fins in the pFET region is made of silicon germanium (SiGe).
12. The device according to claim 9 , wherein the oxide liner comprises SiO 2 disposed between the SiBCN liner and the Si fins.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. Each fin has a silicon nitride (SiN) cap. An oxide liner covers the silicon fins in the nFET region. A silicon dioxide (SiO2) dielectric layer fills the space between the silicon fins, leaving the upper portions exposed. A siliconborocarbonitride (SiBCN) diffusion barrier liner is placed between the oxide liner and the SiO2 dielectric layer, and is also directly on the bottom surface of the SiO2 dielectric layer. The oxide liner is made of SiO2 and is placed between the SiBCN liner and the silicon fins.
13. The device according to claim 12 , wherein the SiO 2 liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. Each fin has a silicon nitride (SiN) cap. An oxide liner covers the silicon fins in the nFET region. A silicon dioxide (SiO2) dielectric layer fills the space between the silicon fins, leaving the upper portions exposed. A siliconborocarbonitride (SiBCN) diffusion barrier liner is placed between the oxide liner and the SiO2 dielectric layer, and is also directly on the bottom surface of the SiO2 dielectric layer. The oxide liner is made of SiO2 and is placed between the SiBCN liner and the silicon fins. The SiO2 liner is 1 nanometer thick on either side of the silicon fins.
14. The device according to claim 8 , further comprising: a SiN liner disposed on the Si fins in the pFET region between the diffusion barrier liner and the Si fins.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. Each fin has a silicon nitride (SiN) cap. An oxide liner covers the silicon fins in the nFET region. A silicon dioxide (SiO2) dielectric layer fills the space between the silicon fins, leaving the upper portions exposed. A diffusion barrier liner is placed between the oxide liner and the SiO2 dielectric layer, and is also directly on the bottom surface of the SiO2 dielectric layer. A silicon nitride (SiN) liner is present on the silicon fins in the pFET region between the diffusion barrier liner and the silicon fins.
15. The device according to claim 8 , wherein the nFET channel region is doped with boron (B).
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. Each fin has a silicon nitride (SiN) cap. An oxide liner covers the silicon fins in the nFET region. A silicon dioxide (SiO2) dielectric layer fills the space between the silicon fins, leaving the upper portions exposed. A diffusion barrier liner is placed between the oxide liner and the SiO2 dielectric layer, and is also directly on the bottom surface of the SiO2 dielectric layer. The nFET channel region is doped with boron.
16. A device comprising: silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, wherein an upper portion of the Si fins in the pFET region comprise silicon germanium (SiGe); a silicon dioxide (SiO 2 ) liner over the Si fins in the nFET region; a SiO 2 dielectric layer disposed between a lower portion of the Si fins, leaving an exposed upper portion of the Si fins; a SiN liner disposed on the Si fins in the pFET region between a diffusion barrier liner and the Si fins; and a siliconborocarbonitride (SiBCN) liner disposed between the SiO 2 liner and the SiO 2 dielectric layer in the nFET region, between the SiN liner and the SiO 2 dielectric layer in the pFET region, and directly on a bottom surface of the SiO 2 dielectric layer.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. The upper portion of the silicon fins in the pFET region is silicon germanium (SiGe). A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region. A SiO2 dielectric layer fills the space between the lower portions of the silicon fins, leaving the upper portions exposed. A silicon nitride (SiN) liner covers the silicon fins in the pFET region, positioned between a diffusion barrier liner and the silicon fins. A siliconborocarbonitride (SiBCN) liner is located between the SiO2 liner and the SiO2 dielectric layer in the nFET region, between the SiN liner and the SiO2 dielectric layer in the pFET region, and directly on the bottom surface of the SiO2 dielectric layer.
17. The device according to claim 16 , wherein the SiO 2 liner in the nFET region is disposed between the SiBCN liner and the Si fins.
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. The upper portion of the silicon fins in the pFET region is silicon germanium (SiGe). A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region. A SiO2 dielectric layer fills the space between the lower portions of the silicon fins, leaving the upper portions exposed. A silicon nitride (SiN) liner covers the silicon fins in the pFET region, positioned between a diffusion barrier liner (SiBCN) and the silicon fins. A siliconborocarbonitride (SiBCN) liner is located between the SiO2 liner and the SiO2 dielectric layer in the nFET region, between the SiN liner and the SiO2 dielectric layer in the pFET region, and directly on the bottom surface of the SiO2 dielectric layer. The SiO2 liner in the nFET region is located between the SiBCN liner and the silicon fins.
18. The device according to claim 17 , wherein the SiO 2 liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.
The invention relates to semiconductor devices, specifically to the structure and fabrication of silicon fin field-effect transistors (FinFETs). A key challenge in FinFET technology is controlling the interface between the silicon fins and the surrounding dielectric materials to ensure optimal electrical performance and reliability. The invention addresses this by incorporating a thin silicon dioxide (SiO2) liner on the opposing sides of the silicon fins. The SiO2 liner serves as a protective and insulating layer, improving the interface quality and reducing leakage currents. The liner has a precisely controlled thickness of 1 nanometer (nm), which balances electrical insulation with minimal impact on the fin dimensions. This thin liner is deposited before forming additional dielectric layers, such as high-k dielectrics or spacers, ensuring a stable interface. The invention also includes methods for forming the SiO2 liner, such as thermal oxidation or chemical vapor deposition, followed by selective etching or deposition of subsequent layers. The resulting FinFET structure exhibits improved gate control, reduced parasitic capacitance, and enhanced reliability, making it suitable for advanced semiconductor manufacturing.
19. The device according to claim 16 , wherein the nFET channel region is doped with boron (B).
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. The upper portion of the silicon fins in the pFET region is silicon germanium (SiGe). A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region. A SiO2 dielectric layer fills the space between the lower portions of the silicon fins, leaving the upper portions exposed. A silicon nitride (SiN) liner covers the silicon fins in the pFET region, positioned between a siliconborocarbonitride (SiBCN) diffusion barrier liner and the silicon fins. A siliconborocarbonitride (SiBCN) liner is located between the SiO2 liner and the SiO2 dielectric layer in the nFET region, between the SiN liner and the SiO2 dielectric layer in the pFET region, and directly on the bottom surface of the SiO2 dielectric layer. The nFET channel region is doped with boron.
20. The device according to claim 16 , wherein the pFET channel region is doped with phosphorous (P).
The device has silicon fins on a substrate, with negative (nFET) and positive (pFET) transistor regions. The upper portion of the silicon fins in the pFET region is silicon germanium (SiGe). A silicon dioxide (SiO2) liner covers the silicon fins in the nFET region. A SiO2 dielectric layer fills the space between the lower portions of the silicon fins, leaving the upper portions exposed. A silicon nitride (SiN) liner covers the silicon fins in the pFET region, positioned between a siliconborocarbonitride (SiBCN) diffusion barrier liner and the silicon fins. A siliconborocarbonitride (SiBCN) liner is located between the SiO2 liner and the SiO2 dielectric layer in the nFET region, between the SiN liner and the SiO2 dielectric layer in the pFET region, and directly on the bottom surface of the SiO2 dielectric layer. The pFET channel region is doped with phosphorous.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 3, 2016
April 4, 2017
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