A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate; a silicon dioxide (SiO 2 ) liner over the Si fins in the nFET region; a dielectric layer disposed between a lower portion of the Si fins, leaving an exposed upper portion of the Si fins; and a siliconborocarbonitride (SiBCN) liner disposed between the SiO 2 liner and the dielectric layer, and directly on a bottom surface of the dielectric layer.
2. The device according to claim 1 , wherein the exposed upper portion of the Si fins in the pFET region comprises silicon germanium (SiGe).
3. The device according to claim 2 , wherein the SiO 2 liner in the nFET region is disposed between the SiBCN liner and the Si fins.
4. The device according to claim 3 , wherein the SiO 2 liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.
5. The device according to claim 1 , further comprising: a SiN liner disposed on the Si fins in the pFET region between the SiBCN liner and the Si fins.
6. The device according to claim 1 , wherein the nFET channel region is doped with boron (B).
7. The device according to claim 1 , wherein the dielectric layer comprises SiO 2 .
8. A device comprising: silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; an oxide liner formed over the Si fins in the nFET region; a silicon dioxide (SiO 2 ) dielectric layer disposed between the Si fins, leaving an exposed upper portion of the Si fins; and a diffusion barrier liner disposed between the oxide liner and the SiO 2 dielectric layer, and directly on a bottom surface of the SiO 2 dielectric layer.
9. The device according to claim 8 , wherein the diffusion barrier liner comprises siliconborocarbonitride (SiBCN).
10. The device according to claim 8 , wherein the SiO 2 dielectric layer is densified by way of annealing.
11. The device according to claim 8 , wherein an upper portion of the Si fins in the pFET region comprise silicon germanium (SiGe).
12. The device according to claim 9 , wherein the oxide liner comprises SiO 2 disposed between the SiBCN liner and the Si fins.
13. The device according to claim 12 , wherein the SiO 2 liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.
14. The device according to claim 8 , further comprising: a SiN liner disposed on the Si fins in the pFET region between the diffusion barrier liner and the Si fins.
15. The device according to claim 8 , wherein the nFET channel region is doped with boron (B).
16. A device comprising: silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, wherein an upper portion of the Si fins in the pFET region comprise silicon germanium (SiGe); a silicon dioxide (SiO 2 ) liner over the Si fins in the nFET region; a SiO 2 dielectric layer disposed between a lower portion of the Si fins, leaving an exposed upper portion of the Si fins; a SiN liner disposed on the Si fins in the pFET region between a diffusion barrier liner and the Si fins; and a siliconborocarbonitride (SiBCN) liner disposed between the SiO 2 liner and the SiO 2 dielectric layer in the nFET region, between the SiN liner and the SiO 2 dielectric layer in the pFET region, and directly on a bottom surface of the SiO 2 dielectric layer.
17. The device according to claim 16 , wherein the SiO 2 liner in the nFET region is disposed between the SiBCN liner and the Si fins.
18. The device according to claim 17 , wherein the SiO 2 liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.
19. The device according to claim 16 , wherein the nFET channel region is doped with boron (B).
20. The device according to claim 16 , wherein the pFET channel region is doped with phosphorous (P).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 3, 2016
April 4, 2017
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