An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhombohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device, comprising: a trigonal crystal substrate defining a (0001) C-plane; a rhombohedrally aligned buffer layer comprising a plurality of rhombohedrally aligned (111)-oriented crystals disposed on the (0001) C-plane of the crystal substrate, wherein the plurality of rhombohedrally aligned (111)-oriented crystals comprise a material selected from the group consisting of group IV semiconductors and alloys of group IV semiconductors; at least one layer comprising a first region disposed on the rhombohedrally aligned buffer layer, the first region comprising a p+doped SiGe layer having a thickness of less than about 100 nm and a secondary region disposed on the first region, the secondary region comprising a p-doped Ge, or intrinsic Ge material to form a quantum well structure for the fast transport of holes, such that the secondary region collects holes from the first region; and wherein additional layers have the first region disposed on the secondary region and the secondary region disposed on the first region.
2. The device of claim 1 , wherein the secondary region has at least two times higher hole mobility than the adjacent first region.
3. The device of claim 1 , wherein the trigonal crystal substrate comprises a Sapphire material.
4. The device of claim 1 , wherein the rhombohedrally aligned (111)-oriented crystals comprise a group IV semiconductor material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 10, 2014
April 4, 2017
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