Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device comprising: a plurality of first terminals; a plurality of second terminals, the second terminals being configured to receive a plurality of first test data in serial in a first test operation and to receive a shift clock signal in a second test operation; a third terminal; a plurality of buffer circuits; a plurality of data input/output lines each coupled between an associated one of the first terminals and an associated one of the buffer circuits; and a plurality of test circuit units, wherein each test circuit unit is coupled to an associated one of the data input/output lines by being connected to the associated data input/output line at a location between the first terminal associated with the associated data input/output line and the buffer circuit associated with the associated data input/output line, the test circuit units being connected in series, wherein in the first test operation, the plurality of first test data are sequentially supplied to the test circuit units, and the test circuit units supply the plurality of first test data to the data input/output lines in parallel, and in the second test operation, a plurality of second test data supplied from the buffer circuits are supplied in parallel to the test circuit units, and the test circuit units serially output the plurality of second test data through the third terminal synchronously with the shift clock signal.
The semiconductor device includes multiple I/O terminals, along with test circuits for write/read testing. It has first terminals, second terminals for serial test data and shift clock input, and a third terminal. Buffer circuits sit between the first terminals and internal circuits, connected by data I/O lines. Test units tap into these I/O lines between the first terminals and the buffers, arranged in series. In write testing, serial test data is loaded into test units and then driven in parallel onto the I/O lines. In read testing, parallel data from the buffers flows into the test units, then is shifted out serially through the third terminal, synchronized by the shift clock.
2. The device as claimed in claim 1 , wherein the second terminals includes a first command address terminal supplied with the plurality of first test data, and a second command address terminal supplied with the shift clock signal, and in the first test operation, the plurality of first test data are serially supplied from outside through the first command address terminal, and the plurality of first test data are sequentially transferred to the test circuit units synchronously with the shift clock signal.
The semiconductor testing system uses specific second terminals: a first terminal for the serial test data and a second terminal for the shift clock signal as described in the previous semiconductor device. During the write test, the serial test data is input through the first command terminal and sequentially propagates through the test units, synchronized to the shift clock signal, as described in the previous semiconductor device.
3. The device as claimed in claim 2 , wherein in the second test operation, a flag signal supplied from the first command address terminal is held by one of the test circuit units, the flag signal is shifted among the test circuit units synchronously with the shift clock signal, and the test circuit unit that has the flag signal held therein supplies an associated one of the plurality of second test data to the third terminal.
Building on the previous serial testing, the read test operation involves using a flag signal. This flag is input via the first command/address terminal and is captured by one of the test circuit units. The flag then shifts between the test units, synchronized with the shift clock, as described in the previous semiconductor device. The test unit currently holding the flag drives its corresponding data value (second test data) to the third terminal.
4. The device as claimed in claim 3 , wherein the first terminals include a plurality of first data input/output terminals and a plurality of second data input/output terminals, the second terminals further includes a third command address terminal supplied with a selection signal, and in the second test operation, the second test data corresponding to one of the first and second data input/output terminals are supplied to the third terminal based on the selection signal.
Expanding on the device's testing capabilities, the first terminals, as described previously, are divided into two sets of data I/O terminals. The second terminals now include a third command terminal, which takes a selection signal. In the read test operation, as described previously, the selection signal determines whether data from the first or second set of data I/O terminals is routed to the third terminal for output.
5. The device as claimed in claim 1 , wherein the test circuit units serially output the plurality of first test data through the third terminal synchronously with the shift clock signal supplied from one of the second terminals in a leak test operation after performing the first test operation.
In addition to the write and read test operations described in the base semiconductor device, a leak test is performed. Following the write test, the test circuit units serially output the first test data through the third terminal, synchronized with the shift clock from one of the second terminals. This test checks for data leakage within the device.
6. The device as claimed in claim 1 , wherein in a normal operation, a plurality of first data supplied in parallel via the first terminals are supplied in parallel to the buffer circuits via the data input/output lines, and second data output in parallel from the buffer circuits via the data input/output lines are output in parallel to the first terminals.
During normal operation (not testing), the semiconductor device functions as a standard I/O. Parallel data arrives at the first terminals and is then passed, in parallel, through the data I/O lines to the buffer circuits. Conversely, data coming from the buffer circuits are driven, in parallel, over the data I/O lines, back to the first terminals for output.
7. The device as claimed in claim 1 , further comprising: a fourth terminal supplied with a clock signal; and a data latch circuit that latches the plurality of first test data in parallel on the data input/output lines synchronously with the clock signal.
The semiconductor device includes a fourth terminal dedicated to a clock signal, as well as a data latch circuit. This latch captures the parallel test data present on the data I/O lines. The data capture by the latch is synchronized with the clock signal received at the fourth terminal during testing.
8. The device as claimed in claim 1 , wherein the first terminals includes a plurality of data terminals and a data strobe terminal.
The first terminals, as described in the base semiconductor device, include multiple data terminals and a data strobe terminal.
9. The device as claimed in claim 1 , wherein the third terminal is a data mask terminal.
The third terminal, used for serial data output during read testing, functions as a data mask terminal.
10. A semiconductor device comprising: a plurality of first terminals; a plurality of second terminals, the second terminals being configured to receive a plurality of first test data in serial in a first test operation and to receive a shift clock signal in a second test operation; a third terminal; a plurality of buffer circuits; a plurality of data input/output lines each coupled between an associated one of the first terminals and an associated one of the buffer circuits; and a plurality of test circuit units each coupled to an associated one of the data input/output lines, the test circuit units being connected in series, wherein in the first test operation, the plurality of first test data are sequentially supplied to the test circuit units, and the test circuit units supply the plurality of first test data to the data input/output lines in parallel, in the second test operation, a plurality of second test data supplied from the buffer circuits are supplied in parallel to the test circuit units, and the test circuit units serially output the plurality of second test data through the third terminal synchronously with the shift clock signal, the second terminals includes a first command address terminal supplied with the plurality of first test data, and a second command address terminal supplied with the shift clock signal, in the first test operation, the plurality of first test data are serially supplied from outside through the first command address terminal, and the plurality of first test data are sequentially transferred to the test circuit units synchronously with the shift clock signal, and in the second test operation, a flag signal supplied from the first command address terminal is held by one of the test circuit units, the flag signal is shifted among the test circuit units synchronously with the shift clock signal, and the test circuit unit that has the flag signal held therein supplies an associated one of the plurality of second test data to the third terminal.
The semiconductor device includes multiple I/O terminals, along with test circuits for write/read testing. It has first terminals, second terminals for serial test data and shift clock input, and a third terminal. Buffer circuits sit between the first terminals and internal circuits, connected by data I/O lines. Test units tap into these I/O lines, arranged in series. In write testing, serial test data is loaded into test units and then driven in parallel onto the I/O lines. In read testing, parallel data from the buffers flows into the test units, then is shifted out serially through the third terminal, synchronized by the shift clock. The second terminals are used for serial test data and shift clock input. During the write test, the serial test data is input through the first command terminal and sequentially propagates through the test units, synchronized to the shift clock signal. In read testing, a flag is input and shifted between test units, with the test unit holding the flag driving its data to the third terminal.
11. The device as claimed in claim 10 , wherein the first terminals include a plurality of first data input/output terminals and a plurality of second data input/output terminals, the second terminals further includes a third command address terminal supplied with a selection signal, and in the second test operation, the second test data corresponding to one of the first and second data input/output terminals are supplied to the third terminal based on the selection signal.
Expanding on the device's testing capabilities, the first terminals, as described previously, are divided into two sets of data I/O terminals. The second terminals now include a third command terminal, which takes a selection signal. In the read test operation, as described previously, the selection signal determines whether data from the first or second set of data I/O terminals is routed to the third terminal for output.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 14, 2013
April 11, 2017
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