A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.
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1. A method for fabricating a semiconductor device comprising: providing a dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer, wherein a top surface of the poly-silicon gate electrode and a top surface of the poly-silicon element layer are coplanar; forming a first spacer on sidewalls of two opposite sides of the dummy gate; forming a second spacer on sidewalls of two opposite sides of the passive device; after forming the first spacer and the second spacer, forming a hard mask layer conformally on the first spacer, the second spacer, the dummy gate and the passive device; performing a first etching process to remove a portion of the hard mask layer and a portion of the poly-silicon element layer to form a recess in the passive device exposing a remaining portion of the poly-silicon element layer; forming an inner layer dielectric (ILD) on the dummy gate and the poly-silicon element layer; flattening the ILD by using the hard mask layer as a polish stop layer; performing a second etching process to remove the poly-silicon gate electrode; and forming a metal gate electrode on the location where the poly-silicon gate electrode was initially disposed.
A method for making semiconductor devices integrates a transistor and a passive device. First, create a dummy gate made of polysilicon and a passive device also using a polysilicon layer, ensuring their top surfaces are level. Next, form spacers on the sides of both the dummy gate and the passive device. Then, deposit a hard mask layer over everything. Etch away parts of the hard mask and the polysilicon layer of the passive device, creating a recess that exposes some of the polysilicon. After that, deposit an insulating layer (ILD) over the dummy gate and the passive device. Polish the ILD, using the hard mask as a stopping point to ensure a flat surface. Remove the polysilicon from the dummy gate area using etching. Finally, deposit a metal gate in the space where the dummy gate was.
2. The method for fabricating the semiconductor device according to claim 1 , wherein the formation of the dummy gate and the passive device comprises: providing a dielectric material layer and a poly-silicon layer stacked in sequence on a substrate; and patterning the dielectric material layer and the poly-silicon layer to form the poly-silicon gate electrode and the poly-silicon element layer on the patterned dielectric material layer.
In the method for fabricating a semiconductor device involving a dummy gate and a passive device, a key step involves creating these initial structures. Start by depositing a dielectric material and a polysilicon layer on a substrate. Then, pattern both layers to form the polysilicon gate electrode of the dummy gate and the polysilicon element layer of the passive device on top of the patterned dielectric. This patterning defines the initial shape and location of both the transistor gate and the passive device element before subsequent processing steps like spacer formation and etching, as described in the method where a dummy gate and a passive device are provided, spacers are formed, a hard mask layer is deposited, etching is performed, an ILD layer is formed and flattened, and a metal gate is formed.
3. The method for fabricating the semiconductor device according to claim 2 , wherein the dielectric material layer comprises an interfacial layer (IL) and a high-k dielectric layer stacked in sequence on the substrate.
The method for fabricating a semiconductor device, which includes creating a dummy gate and a passive device by depositing and patterning a dielectric material layer and a polysilicon layer, specifies the composition of the dielectric material. Instead of a simple dielectric, use a stack of two layers: an interfacial layer (IL) directly on the substrate, followed by a high-k dielectric layer on top of the IL. This dielectric stack is then patterned along with the polysilicon layer to create the gate dielectric for the transistor. This approach enhances the electrical performance of the resulting semiconductor device.
4. The method for fabricating the semiconductor device according to claim 3 , further comprising steps of forming a capping layer disposed between the metal gate electrode and high-k dielectric layer.
In the method for fabricating a semiconductor device including a dummy gate and a passive device, and which uses a dielectric stack (interfacial layer and high-k dielectric), an additional layer is added between the high-k dielectric and the final metal gate. This is a capping layer. This layer is formed *after* removing the dummy gate and *before* depositing the metal gate electrode. This capping layer helps optimize the interface between the high-k dielectric and the metal gate, further improving device performance characteristics such as threshold voltage stability.
5. The method for fabricating the semiconductor device according to claim 4 , further comprising steps of forming a working function layer on the capping layer, prior to the formation of the metal gate electrode.
The method for fabricating a semiconductor device that uses a dummy gate, a passive device, a high-k dielectric layer, and a capping layer, includes yet another layer to fine-tune transistor properties. After forming the capping layer *and before* depositing the metal gate electrode, a work function layer is created on the capping layer. This working function layer directly influences the transistor's threshold voltage, allowing for precise control over its switching behavior. The metal gate electrode is subsequently formed on the working function layer.
6. The method for fabricating the semiconductor device according to claim 2 , further comprising steps of forming a source/drain structure by using the dummy gate as a mask, before the second etching process is carried out.
In the method for fabricating a semiconductor device involving a dummy gate, a passive device, dielectric layers, and polysilicon layers, a source/drain structure is created *before* the dummy gate is removed and replaced with a metal gate. This is achieved by using the dummy gate itself as a mask during source/drain implantation or diffusion. This self-aligned process ensures accurate placement of the source/drain regions relative to the gate, minimizing parasitic capacitance and improving transistor speed. After source/drain formation, the dummy gate is etched away, and the metal gate is deposited.
7. The method for fabricating the semiconductor device according to claim 2 , prior to the formation of the metal gate electrode, further comprising: forming a high-k dielectric layer on the location where the poly-silicon gate electrode was initially disposed; and forming at least one working function layer on the high-k dielectric layer.
In the method for fabricating a semiconductor device involving a dummy gate, a passive device, dielectric layers, and polysilicon layers, the final gate stack is carefully constructed. *Before* forming the metal gate electrode, a high-k dielectric layer is deposited in the space where the polysilicon gate electrode was originally located. *Then*, at least one work function layer is deposited on top of this high-k dielectric layer. This multi-layer gate dielectric and work function stack allows for fine-tuning of the transistor's electrical characteristics, such as threshold voltage, independent of the metal gate material. The metal gate is then formed on top.
8. The method for fabricating the semiconductor device according to claim 1 , wherein the second etching process comprises a wet etching and a dry etching.
In the method for fabricating a semiconductor device that makes a dummy gate and passive device, deposits a hard mask, etches, forms an ILD, and deposits a metal gate, the removal of the polysilicon gate electrode (the "second etching process") is performed in two steps: first, a wet etch is used to remove the bulk of the polysilicon, followed by a dry etch to remove any remaining residue and ensure a clean surface for the subsequent metal gate deposition. This combination of wet and dry etching provides both high throughput and excellent surface quality.
9. The method for fabricating the semiconductor device according to claim 1 , wherein the steps of flattening the ILD comprise a chemical mechanism polishing (CMP) process.
In the method for fabricating a semiconductor device that makes a dummy gate and passive device, deposits a hard mask, etches, forms an ILD, and deposits a metal gate, the step of flattening the inner layer dielectric (ILD) uses a Chemical Mechanical Polishing (CMP) process. CMP uses a combination of chemical etchants and mechanical abrasion to achieve a highly planar surface. The hard mask layer acts as a polish stop, ensuring that the ILD is polished down to a precise level, creating a flat surface for subsequent processing steps.
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December 11, 2013
April 11, 2017
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