A semiconductor memory device includes a plurality of memory cells arranged in rows and columns; a source line electrically connected to one terminal of each of the memory cells; a bit line electrically connected to the other terminal of each of the memory cells; a plurality of first word lines, each electrically connected to memory cells included in corresponding one of the rows; and a plurality of second word lines, each electrically connected to memory cells included in corresponding one of the columns. Each of the memory cells includes a first selection transistor including a current path having one end electrically connected to the source line; a second selection transistor including a current path having one end electrically connected to the other end of the current path of the first selection transistor; and a variable resistance element including a current path having one end electrically connected to the other end of the current path of the second selection transistor, and the other end electrically connected to the bit line.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor memory device comprising: a plurality of memory cells arranged in rows and columns; a source line electrically connected to one terminal of each of the memory cells; a bit line electrically connected to the other terminal of each of the memory cells; a plurality of first word lines, each electrically connected to memory cells included in a corresponding one of the rows; and a plurality of second word lines, each electrically connected to memory cells included in a corresponding one of the columns; wherein each of the memory cells comprises: a first selection transistor including a current path having one end electrically connected to the source line; a second selection transistor including a current path having one end electrically connected to the other end of the current path of the first selection transistor; and a variable resistance element including a current path having one end electrically connected to the other end of the current path of the second selection transistor, and the other end electrically connected to the bit line.
A semiconductor memory device comprises a grid of memory cells arranged in rows and columns. Each memory cell has one terminal connected to a shared source line and the other to a bit line. Rows are controlled by first word lines, and columns by second word lines. Each memory cell consists of a first selection transistor connected to the source line, a second selection transistor connected to the first, and a variable resistance element (like a memristor) connected between the second transistor and the bit line. Activating both selection transistors allows current to flow through the variable resistance element, enabling read/write operations.
2. The device of claim 1 , wherein the variable resistance element comprises: a storage layer as a ferromagnetic layer having a variable magnetization direction; a reference layer as a ferromagnetic layer having an invariable magnetization direction; and a tunnel barrier layer as a nonmagnetic layer formed between the storage layer and the reference layer.
The semiconductor memory device as described where each memory cell has a variable resistance element. The variable resistance element is implemented using a magnetic tunnel junction (MTJ) structure. This MTJ consists of a storage layer (ferromagnetic with variable magnetization), a reference layer (ferromagnetic with fixed magnetization), and a thin, non-magnetic tunnel barrier layer between them. The resistance of the element changes based on the relative magnetization directions of the storage and reference layers, enabling data storage.
3. The device of claim 1 , wherein each of the first word lines is electrically connected to a first gate electrode of the first selection transistor included in each of the memory cells included in the corresponding one of the rows, and each of the second word lines is electrically connected to a second gate electrode of the second selection transistor included in each of the memory cells included in the corresponding one of the columns.
In the semiconductor memory device, each first word line connects directly to the first gate electrode of the first selection transistor in its corresponding row of memory cells. Similarly, each second word line connects directly to the second gate electrode of the second selection transistor in its corresponding column. This allows each word line to selectively activate the transistors within its row or column for memory access.
4. The device of claim 3 , wherein the device includes a semiconductor substrate including a plane portion extending in a first direction and a second direction perpendicular to the first direction, and pillar portions formed on an upper surface of the plane portion and extending in a stacking direction, the first direction corresponding to an extending direction of each of the rows and the second direction corresponding to an extending direction of each of the columns, wherein: the source line corresponds to the plane portion, with respect to each of the memory cells: the first gate electrode is formed on a first gate insulating layer on a lower side surface of a corresponding one of the pillar portions, the second gate electrode is formed on a second gate insulating layer on an upper side surface of the pillar portion, the variable-resistance element is formed on an upper surface of the pillar portion, and the bit line is formed on an upper surface of the variable resistance element, the first gate electrodes extend in the first direction to form the first word lines, and the second gate electrodes extend in the second direction to form the second word lines.
The semiconductor memory device is built on a semiconductor substrate. The substrate has a flat area, and vertical pillar structures rise from it. Rows run along the flat area, and columns are perpendicular. The source line is the flat substrate. In each cell, the first transistor's gate sits on the lower side of the pillar, and the second's gate is on the upper side. The variable resistance element is on top of the pillar, with the bit line above it. Row word lines are formed by the first transistor gates, column word lines by the second.
5. The device of claim 3 , wherein the device includes a semiconductor substrate including a plane portion extending in a first direction and a second direction perpendicular to the first direction, fin portions formed on an upper surface of the plane portion and extending in the first direction and a stacking direction, and pillar portions formed on upper surfaces of the fin portions and extending in the stacking direction, the first direction corresponding to an extending direction of each of the rows and the second direction corresponding to an extending direction of each of the columns, wherein: the source line corresponds to the plane portion, with respect to each of the memory cells: the first gate electrode is formed on a first gate insulating layer on a side surface of a corresponding one of the fin portions, the second gate electrode is formed on a second gate insulating layer on a side surface of the pillar portion that is on the fin portion, and the variable-resistance element is formed on an upper surface of the pillar portion, and the bit line is formed on an upper surface of the variable resistance element, the first gate electrodes extend in the first direction to form the first word lines, and the second gate electrodes extend in the second direction to form the second word lines.
The semiconductor memory device is built on a semiconductor substrate with fin-shaped structures (fins) and vertical pillar structures on top of the fins. Rows run along the fins' length, and columns are perpendicular. The source line is the flat substrate. In each cell, the first transistor's gate is on the fin's side, and the second's gate is on the pillar's side (atop the fin). The variable resistance element is on top of the pillar, with the bit line above it. Row word lines are formed by the first transistor gates, column word lines by the second.
6. The device of claim 1 , wherein when a write operation or a read operation is performed on the variable resistance element included in a desired one of the memory cells, a voltage to turn on the first selection transistor included in the desired one of the memory cells is applied to one of the first word lines which is electrically connected to the desired one of the memory cells, a voltage to turn on the second selection transistor included in the desired one of the memory cells is applied to one of the second word lines which is electrically connected to the desired one of the memory cells, and a potential difference is produced between the source line and the bit line.
The semiconductor memory device's write or read operations target a specific memory cell's variable resistance element. To access it, a voltage turns on the first transistor through the appropriate row word line and the second transistor through the appropriate column word line. This creates a potential difference between the source and bit lines, allowing current to flow and modify or sense the resistance of the selected memory cell.
7. A semiconductor memory device comprising: first, second, third, fourth, fifth, sixth, seventh, eighth and ninth memory cells arranged in rows and columns, the first, second, and third memory cells being arranged serially along a first row, the fourth, fifth, and sixth memory cells being arranged serially along a second row adjacent to the first row, the seventh, eighth, and ninth memory cells being arranged serially along a third row adjacent to the second row, the first, fourth, and seventh memory cells being arranged serially along a first column, the second, fifth, and eighth memory cells being arranged serially along a second column adjacent to the first column, and the third, sixth, and ninth memory cells being arranged serially along a third column adjacent to the second column; a source line electrically connected to one terminal of each of the first to ninth memory cells; a bit line electrically connected to the other terminal of each of the first to ninth memory cells; first, second, and third word lines, the first word line being electrically connected to the first, second, and third memory cells, the second word line being electrically connected to the fourth, fifth, and sixth memory cells, and the third word line being electrically connected to the seventh, eighth, and ninth memory cells, and fourth, fifth, and sixth word lines; the fourth word line being electrically connected to the first, fourth, and seventh memory cells, the fifth word line being electrically connected to the second, fifth, and eighth memory cells, and the sixth word line being electrically connected to the third, sixth, and ninth memory cells, wherein each of the first to ninth memory cells comprises: a first selection transistor including a current path having one end electrically connected to the source line; a second selection transistor including a current path having one end electrically connected to the other end of the current path of the first selection transistor; and a variable resistance element including a current path having one end electrically connected to the other end of the current path of the second selection transistor, and the other end electrically connected to the bit line.
A semiconductor memory device comprises a 3x3 grid of memory cells. Each cell has one terminal connected to a shared source line and the other to a bit line. Three word lines control the rows, and three others control the columns. Each memory cell has a first selection transistor connected to the source line, a second selection transistor connected to the first, and a variable resistance element connected between the second transistor and the bit line. Activating both selection transistors in a specific cell allows current to flow through the variable resistance element, enabling read/write operations.
8. The device of claim 7 , wherein the variable resistance element comprises: a storage layer as a ferromagnetic layer having a variable magnetization direction; a reference layer as a ferromagnetic layer having an invariable magnetization direction; and a tunnel barrier layer as a nonmagnetic layer formed between the storage layer and the reference layer.
The 3x3 semiconductor memory device has variable resistance elements within each memory cell. These elements are magnetic tunnel junctions (MTJs), each with a storage layer (ferromagnetic, variable magnetization), a reference layer (ferromagnetic, fixed magnetization), and a non-magnetic tunnel barrier between them. The resistance changes with the magnetic orientation between layers, storing data.
9. The device of claim 7 , wherein the first word line is electrically connected to a first gate electrode of the first selection transistor included in each of the first, second, and third memory cells, the second word line is electrically connected to a first gate electrode of the first selection transistor included in each of the fourth, fifth, and sixth memory cells, the third word line is electrically connected to a first gate electrode of the first selection transistor included in each of the seventh, eighth, and ninth memory cells, the fourth word line is electrically connected to a second gate electrode of the second selection transistor included in each of the first, fourth, and seventh memory cells, the fifth word line is electrically connected to a second gate electrode of the second selection transistor included in each of the second, fifth, and eighth memory cells, and the sixth word line is electrically connected to a second gate electrode of the second selection transistor included in each of the third, sixth, and ninth memory cells.
In the 3x3 semiconductor memory device, the row word lines connect to the first gate of the first transistor for each cell in that row. The column word lines connect to the second gate of the second transistor for each cell in that column. This allows precise selection of individual cells by activating both transistors for read/write operations.
10. The device of claim 9 , wherein the device includes a semiconductor substrate including a plane portion extending in a first direction and a second direction perpendicular to the first direction, and pillar portions formed on an upper surface of the plane portion and extending in a stacking direction, the first direction corresponding to an extending direction of each of the first, second and third rows and the second direction corresponding to an extending direction of each of the first, second and third columns, wherein: the source line corresponds to the plane portion, with respect to each of the first to ninth memory cells: the first gate electrode is formed on a first gate insulating layer on a lower side surface of a corresponding one of the pillar portions, the second gate electrode is formed on a second gate insulating layer on an upper side surface of the pillar portion, the variable-resistance element is formed on an upper surface of the pillar portion, and the bit line is formed on an upper surface of the variable resistance element, the first gate electrodes extend in the first direction to form the first, second, and third word lines, and the second gate electrodes extend in the second direction to form the fourth, fifth, and sixth word lines.
The 3x3 semiconductor memory device is fabricated on a substrate with a flat area and pillar structures. Rows and columns run along the flat area. The source line is the flat area. In each cell, the first transistor's gate is on the pillar's lower side, and the second's gate is on the pillar's upper side. The variable resistance element is on the pillar's top, and the bit line above that. Row word lines connect to the first transistor gates; column word lines connect to the second.
11. The device of claim 9 , wherein the device includes a semiconductor substrate including a plane portion extending in a first direction and a second direction perpendicular to the first direction, fin portions formed on an upper surface of the plane portion and extending in the first direction and a stacking direction, and pillar portions formed on upper surfaces of the fin portions and extending in the stacking direction, the first direction corresponding to an extending direction of each of the first, second and third rows and the second direction corresponding to an extending direction of each of the first, second and third columns, wherein: the source line corresponds to the plane portion, with respect to each of the first to ninth memory cells, the first gate electrode is formed on a first gate insulating layer on a side surface of the fin portion, the second gate electrode is formed on a second gate insulating layer on a side surface of the pillar portion that is on the fin portion portion, the variable-resistance element is formed on an upper surface of the pillar portion, and the bit line is formed on an upper surface of the variable resistance element, the first gate electrodes extend in the first direction to form the first, second, and third word lines, and the second gate electrodes extend in the second direction to form the fourth, fifth, and sixth word lines.
The 3x3 semiconductor memory device is constructed on a substrate with fins and pillars. Rows are along the fins, columns are perpendicular. The source line is the flat area. In each cell, the first transistor's gate is on the fin's side, and the second's gate is on the pillar's side (atop the fin). The variable resistance element is on the pillar's top, with the bit line above. Row word lines connect to the first transistor gates; column word lines connect to the second.
12. The device of claim 7 , wherein when a write operation or a read operation is performed on the variable resistance element included in a desired one of the first to ninth memory cells, a voltage to turn on the first selection transistor included in the desired one of the first to ninth memory cells is applied to one of the first, second, and third word lines which is electrically connected to the desired one of the first to ninth memory cells, a voltage to turn on the second selection transistor included in the desired one of the first to ninth memory cells is applied to one of the fourth, fifth, and sixth word lines which is electrically connected to the desired one of the first to ninth memory cells, and a potential difference is produced between the source line and the bit line.
In the 3x3 semiconductor memory device, a selected memory cell (1 of 9) is accessed by applying a voltage to turn on the first transistor using a row word line and a voltage to turn on the second transistor using a column word line. This creates a potential difference between the source and bit lines, allowing read/write operations on the selected cell's variable resistance element.
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June 30, 2016
April 11, 2017
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