An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus, comprising: first and second memory modules, located on a circuit board, configured to operate from a first voltage and a second voltage always being an integer multiple of said first voltage; and a power converter employing a switch-mode power train, located on said circuit board, comprising a plurality of switches configured to provide said second voltage to said first and second memory modules from said first voltage by controlling a plurality of switching frequencies of the plurality of switches, wherein at least one of the plurality of switches is coupled to a capacitor configured to store said second voltage, and wherein path resistances associated with circuit board traces on said circuit board from said power converter to said first and second memory modules are substantially balanced.
This apparatus consists of a circuit board with two memory modules that operate using two different voltages. The second voltage is always a multiple of the first. A power converter, using switch-mode power conversion, is also located on the circuit board. It uses multiple switches, controlled by varying their switching frequencies, to convert the first voltage into the second voltage needed by the memory modules. At least one switch is connected to a capacitor that stores the second voltage. Crucially, the electrical resistance of the circuit board traces connecting the power converter to each memory module is nearly identical, ensuring balanced power delivery.
2. The apparatus as recited in claim 1 wherein said first voltage represents an input voltage to said power converter and said second voltage represents an output voltage of said power converter.
The apparatus from the previous description of two memory modules, a power converter, and balanced trace resistances, specifies that the "first voltage" mentioned is the input voltage to the power converter, and the "second voltage" is the output voltage produced by the power converter and used by the memory modules.
3. The apparatus as recited in claim 1 wherein a voltage drop between said power converter and said first and second memory modules is substantially equal.
The apparatus from the initial description involving two memory modules, a power converter, and balanced trace resistances, is designed so the voltage drop between the power converter's output and each of the two memory modules is almost the same. This ensures both modules receive nearly identical voltage levels.
4. The apparatus as recited in claim 1 wherein said power converter is substantially centrally located on said circuit board.
In the apparatus described previously, containing two memory modules, a power converter, and balanced trace resistances, the power converter is placed in approximately the center of the circuit board.
5. The apparatus as recited in claim 1 wherein said power converter is operable in a light-load mode of operation with a switching frequency dependent on a current drain of said first and second memory modules at said second voltage.
Concerning the previously described apparatus with two memory modules, a power converter, and balanced trace resistances, the power converter can operate in a low-power mode when the memory modules aren't drawing much current. In this light-load mode, the switching frequency of the converter is adjusted based on how much current the memory modules are using at the second voltage.
6. The apparatus as recited in claim 1 wherein the plurality of power switches of said switch-mode power train are alternately enabled to conduct to provide said second voltage as an output voltage of said power converter.
With reference to the apparatus previously described, including two memory modules, a power converter, and balanced trace resistances, the power converter’s switches turn on and off in an alternating sequence to create the second voltage that it outputs.
7. The apparatus as recited in claim 1 wherein said power converter is embodied in a silicon die coupled to a leadframe through solder bumps.
The apparatus described previously, which contains two memory modules, a power converter, and balanced trace resistances, has a power converter that's built on a silicon die. The silicon die is connected to a leadframe using solder bumps to make the electrical connections.
8. The apparatus as recited in claim 7 wherein said solder bumps are copper.
As a refinement to the apparatus from the previous description, where the power converter is constructed from a silicon die connected to a leadframe with solder bumps, the solder bumps are made of copper.
9. The apparatus as recited in claim 1 wherein said integer multiple is always one-half.
Referring back to the original apparatus description featuring two memory modules, a power converter, and balanced trace resistances, the "integer multiple" relating the first and second voltages is always one-half. In other words, the second voltage is always half the value of the first voltage.
10. The apparatus as recited in claim 1 wherein said first and second memory modules are digital random-access memory modules.
The previously described apparatus consisting of two memory modules, a power converter, and balanced trace resistances, utilizes digital random-access memory (RAM) modules.
11. A method, comprising: providing a first voltage to first and second memory modules located on a circuit board; and providing a second voltage always being a one-half integer multiple of said first voltage to said first and second memory modules with a power converter employing a switch-mode power train located on said circuit board, wherein path resistances associated with circuit board traces on said circuit board from said power converter to said first and second memory modules are substantially balanced.
This method involves supplying a first voltage to two memory modules that are located on a circuit board. Also, a second voltage, which is always one-half of the first voltage, is supplied to the memory modules using a power converter that employs a switch-mode power train. This power converter is also located on the circuit board. The electrical resistance of the circuit board traces from the power converter to each of the memory modules is designed to be very similar, ensuring balanced power distribution.
12. The method as recited in claim 11 wherein said first voltage represents an input voltage to said power converter and said second voltage represents an output voltage of said power converter.
The method of supplying power to two memory modules at two voltages using a power converter, and ensuring balanced trace resistances, specifies that the "first voltage" is the input voltage to the power converter, and the "second voltage" is the output voltage of the power converter that the memory modules utilize.
13. The method as recited in claim 11 wherein a voltage drop between said power converter and said first and second memory modules is substantially equal.
The method described previously, involving supplying power to two memory modules with balanced trace resistances, aims to keep the voltage drop between the power converter and each of the memory modules virtually the same.
14. The method as recited in claim 11 wherein said power converter is substantially centrally located on said circuit board.
According to the method defined previously, for supplying power to two memory modules with balanced trace resistances, the power converter is positioned near the center of the circuit board.
15. The method as recited in claim 11 further comprising operating said power converter in a light-load mode of operation with a switching frequency dependent on a current drain of said first and second memory modules at said second voltage.
In addition to the previously described method of supplying power to two memory modules and balancing trace resistances, the power converter can operate in a light-load mode when the memory modules are drawing minimal current. The switching frequency in this mode is adjusted based on the current demand of the memory modules at the second voltage.
16. The method as recited in claim 11 further comprising alternately enabling conduction of power switches of said switch-mode power train to provide said second voltage as an output voltage of said power converter.
Complementing the previously outlined method of supplying power to two memory modules and balancing trace resistances, the method involves alternating the conduction of the power switches within the switch-mode power train to produce the second voltage that serves as the output of the power converter.
17. The method as recited in claim 11 wherein said power converter is embodied in a silicon die coupled to a leadframe through solder bumps.
Regarding the earlier description of the method for supplying power to two memory modules with balanced trace resistances, the power converter is constructed as a silicon die which connects to a leadframe using solder bumps.
18. The method as recited in claim 17 wherein said solder bumps are copper.
In the method mentioned previously where the power converter consists of a silicon die connected to a leadframe using solder bumps, the solder bumps consist of copper.
19. The method as recited in claim 11 wherein said first and second memory modules are digital random-access memory modules.
In the method previously described, where power is supplied to two memory modules with balanced trace resistances, the memory modules are digital random-access memory modules.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 2, 2014
April 18, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.