Patentable/Patents/US-9627307
US-9627307

Semiconductor package and fabrication method thereof

PublishedApril 18, 2017
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Patent Claims
10 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A semiconductor package, comprising: an insulating base body having a first surface with an opening formed therein and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces, wherein the electronic element is disposed in the opening of the insulating base body with the inactive surface of the electronic element facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element.

2

2. The package of claim 1 , wherein the insulating base body is made of silicon oxide or silicon nitride.

3

3. The package of claim 1 , wherein the insulating extending body is made of silicon oxide or silicon nitride.

4

4. The package of claim 1 , wherein the insulating extending body and the insulating base body are integrally formed.

5

5. The package of claim 1 , wherein the inactive surface of the electronic element is bonded to the opening of the insulating base body through a bonding layer.

6

6. The package of claim 1 , wherein the inactive surface of the electronic element is exposed from the second surface of the insulating base body.

7

7. The package of claim 1 , wherein a portion of the circuit layer penetrates the dielectric layer so as to be exposed from the insulating extending body.

8

8. The package of claim 1 , further comprising an RDL (redistribution layer) structure formed on the dielectric layer and the circuit layer and electrically connected to the circuit layer.

9

9. The package of claim 8 , further comprising a packaging substrate disposed on and electrically connected to the RDL structure.

10

10. The package of claim 1 , further comprising a packaging substrate disposed on and electrically connected to the circuit layer.

Classification Codes (CPC)

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Patent Metadata

Filing Date

October 22, 2015

Publication Date

April 18, 2017

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Cite as: Patentable. “Semiconductor package and fabrication method thereof” (US-9627307). https://patentable.app/patents/US-9627307

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