A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.
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1. A semiconductor package, comprising: an insulating base body having a first surface with an opening formed therein and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces, wherein the electronic element is disposed in the opening of the insulating base body with the inactive surface of the electronic element facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element.
A semiconductor package includes an insulating base with a top surface containing an opening and a bottom surface opposite the top. An insulating extension extends outward from the top surface edge of the base, and is thinner than the base. An electronic element, such as a chip, sits in the base's opening, with its inactive side (e.g., backside) facing the base. A dielectric layer covers the opening in the base, the base's top surface, the extension, and the active surface (e.g., frontside) of the electronic element. A circuit layer, with conductive traces, sits on the dielectric layer and makes electrical connections to the electronic element.
2. The package of claim 1 , wherein the insulating base body is made of silicon oxide or silicon nitride.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, and a circuit layer connecting to the element, uses silicon oxide or silicon nitride as the material for the insulating base.
3. The package of claim 1 , wherein the insulating extending body is made of silicon oxide or silicon nitride.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, and a circuit layer connecting to the element, uses silicon oxide or silicon nitride as the material for the insulating extending body.
4. The package of claim 1 , wherein the insulating extending body and the insulating base body are integrally formed.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, and a circuit layer connecting to the element, has the insulating base and the insulating extension formed as a single, integrated piece.
5. The package of claim 1 , wherein the inactive surface of the electronic element is bonded to the opening of the insulating base body through a bonding layer.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, and a circuit layer connecting to the element, includes a bonding layer between the inactive surface of the electronic element and the inside surface of the opening in the insulating base, joining the two parts.
6. The package of claim 1 , wherein the inactive surface of the electronic element is exposed from the second surface of the insulating base body.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, and a circuit layer connecting to the element, has the inactive surface of the electronic element exposed on the bottom surface of the insulating base.
7. The package of claim 1 , wherein a portion of the circuit layer penetrates the dielectric layer so as to be exposed from the insulating extending body.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, and a circuit layer connecting to the element, has portions of the circuit layer passing through the dielectric layer, so that these portions are exposed on the surface of the insulating extension.
8. The package of claim 1 , further comprising an RDL (redistribution layer) structure formed on the dielectric layer and the circuit layer and electrically connected to the circuit layer.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, and a circuit layer connecting to the element, also has a redistribution layer (RDL) formed on top of the dielectric layer and the circuit layer. This RDL structure is electrically connected to the circuit layer, allowing for rerouting of electrical signals.
9. The package of claim 8 , further comprising a packaging substrate disposed on and electrically connected to the RDL structure.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, a circuit layer connecting to the element, and a redistribution layer (RDL) formed on top of the dielectric layer and the circuit layer and electrically connected to the circuit layer, further includes a packaging substrate. This substrate is located on top of and electrically connected to the RDL structure, providing a base for mounting the package to another circuit board.
10. The package of claim 1 , further comprising a packaging substrate disposed on and electrically connected to the circuit layer.
The semiconductor package, which includes an insulating base with an opening, a thinner insulating extension, an electronic element in the opening, a dielectric layer covering everything, and a circuit layer connecting to the element, further includes a packaging substrate. This packaging substrate is disposed on top of, and electrically connected to, the circuit layer, providing a mounting base for the semiconductor package.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 22, 2015
April 18, 2017
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