A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.
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1. A nonvolatile memory (NVM) cell, comprising: a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the first OD region from the second OD region, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; a memory P well in the semiconductor substrate, wherein the memory P well overlaps with the first OD region and the second OD region, and wherein the memory P well has a junction depth that is deeper than the trench depth of the isolation region, and wherein the memory P well has a continuous well structure between the first OD region and the second OD region; a memory N well in the memory P well, wherein the memory N well merely overlaps with the first OD region, and wherein the memory N well has a junction depth that is shallower than the trench depth of the isolation region; and an N + pickup in the memory N well.
The nonvolatile memory (NVM) cell consists of a semiconductor substrate with a first and second OD (presumably diffusion) region separated by an isolation region. The isolation region has a specific trench depth. A PMOS select transistor and a PMOS floating gate transistor are both located on the first OD region and are connected in series. The PMOS floating gate transistor includes a floating gate that sits above the first OD region. A memory P well, located in the substrate, covers both OD regions and has a junction depth deeper than the isolation region's trench depth; it forms a continuous well between the two OD regions. Inside this P well is a memory N well, which only overlaps the first OD region and has a junction depth shallower than the trench depth. An N+ pickup is located within the memory N well, acting as a contact.
2. The NVM cell according to claim 1 , wherein the PMOS select transistor and the PMOS floating gate transistor commonly share the memory N well.
The nonvolatile memory (NVM) cell, which includes a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the first OD region from the second OD region, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; a memory P well in the semiconductor substrate, wherein the memory P well overlaps with the first OD region and the second OD region, and wherein the memory P well has a junction depth that is deeper than the trench depth of the isolation region, and wherein the memory P well has a continuous well structure between the first OD region and the second OD region; a memory N well in the memory P well, wherein the memory N well merely overlaps with the first OD region, and wherein the memory N well has a junction depth that is shallower than the trench depth of the isolation region; and an N + pickup in the memory N well, is configured such that the PMOS select transistor and the PMOS floating gate transistor share the same memory N well.
3. The NVM cell according to claim 1 , wherein the PMOS select transistor comprises a P + source doping region in the memory N well, a common P + doping region spaced apart from the p + source doping region, a select gate channel region near a main surface of the semiconductor substrate between the P + source doping region and the common P + doping region, a select gate overlying the select gate channel region, and a gate dielectric layer between the select gate and the select gate channel region.
The nonvolatile memory (NVM) cell, which includes a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the first OD region from the second OD region, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; a memory P well in the semiconductor substrate, wherein the memory P well overlaps with the first OD region and the second OD region, and wherein the memory P well has a junction depth that is deeper than the trench depth of the isolation region, and wherein the memory P well has a continuous well structure between the first OD region and the second OD region; a memory N well in the memory P well, wherein the memory N well merely overlaps with the first OD region, and wherein the memory N well has a junction depth that is shallower than the trench depth of the isolation region; and an N + pickup in the memory N well, implements the PMOS select transistor with a P+ source doping region in the memory N well, a common P+ doping region spaced away from this source, a select gate channel region at the substrate surface between the two P+ regions, a select gate above this channel, and a gate dielectric separating them.
4. The NVM cell according to claim 3 , wherein the P + source doping region is coupled to a source line SL.
The nonvolatile memory (NVM) cell where the PMOS select transistor comprises a P + source doping region in the memory N well, a common P + doping region spaced apart from the p + source doping region, a select gate channel region near a main surface of the semiconductor substrate between the P + source doping region and the common P + doping region, a select gate overlying the select gate channel region, and a gate dielectric layer between the select gate and the select gate channel region (part of a cell including a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the OD regions, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor disposed on the first OD region with a floating gate overlying the region; a memory P well in the substrate overlapping both OD regions, with a junction depth greater than the trench depth and a continuous well structure between the OD regions; a memory N well in the P well only overlapping the first OD region, with a junction depth less than the trench depth; and an N + pickup in the N well) connects the P+ source doping region of the select transistor to a source line (SL).
5. The NVM cell according to claim 1 , wherein the PMOS floating gate transistor further comprises a common P + doping region on one side of the floating gate, a P + drain doping region on the other side of the floating gate, a floating gate channel region between the common P + doping region and the P + drain doping region, and a gate dielectric layer between the floating gate and the floating gate channel region.
The nonvolatile memory (NVM) cell, which includes a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the first OD region from the second OD region, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; a memory P well in the semiconductor substrate, wherein the memory P well overlaps with the first OD region and the second OD region, and wherein the memory P well has a junction depth that is deeper than the trench depth of the isolation region, and wherein the memory P well has a continuous well structure between the first OD region and the second OD region; a memory N well in the memory P well, wherein the memory N well merely overlaps with the first OD region, and wherein the memory N well has a junction depth that is shallower than the trench depth of the isolation region; and an N + pickup in the memory N well, implements the PMOS floating gate transistor with a common P+ doping region on one side of the floating gate, a P+ drain doping region on the other side, a floating gate channel region between these regions, and a gate dielectric separating the floating gate from the channel.
6. The NVM cell according to claim 5 , wherein the P + drain doping region is coupled to a bit line BL.
The nonvolatile memory (NVM) cell where the PMOS floating gate transistor further comprises a common P + doping region on one side of the floating gate, a P + drain doping region on the other side of the floating gate, a floating gate channel region between the common P + doping region and the P + drain doping region, and a gate dielectric layer between the floating gate and the floating gate channel region (part of a cell including a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the OD regions, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor disposed on the first OD region with a floating gate overlying the region; a memory P well in the substrate overlapping both OD regions, with a junction depth greater than the trench depth and a continuous well structure between the OD regions; a memory N well in the P well only overlapping the first OD region, with a junction depth less than the trench depth; and an N + pickup in the N well) connects the P+ drain doping region to a bit line (BL).
7. The NVM cell according to claim 1 , wherein the PMOS floating gate transistor serves as a charge storage element of the NVM cell.
In the nonvolatile memory (NVM) cell, which includes a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the first OD region from the second OD region, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; a memory P well in the semiconductor substrate, wherein the memory P well overlaps with the first OD region and the second OD region, and wherein the memory P well has a junction depth that is deeper than the trench depth of the isolation region, and wherein the memory P well has a continuous well structure between the first OD region and the second OD region; a memory N well in the memory P well, wherein the memory N well merely overlaps with the first OD region, and wherein the memory N well has a junction depth that is shallower than the trench depth of the isolation region; and an N + pickup in the memory N well, the PMOS floating gate transistor stores the charge representing the memory cell's data.
8. The NVM cell according to claim 1 further comprising a floating gate extension continuously extended from the floating gate to the second OD region and is adjacent to an erase gate (EG) region in the second OD region.
The nonvolatile memory (NVM) cell, which includes a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the first OD region from the second OD region, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; a memory P well in the semiconductor substrate, wherein the memory P well overlaps with the first OD region and the second OD region, and wherein the memory P well has a junction depth that is deeper than the trench depth of the isolation region, and wherein the memory P well has a continuous well structure between the first OD region and the second OD region; a memory N well in the memory P well, wherein the memory N well merely overlaps with the first OD region, and wherein the memory N well has a junction depth that is shallower than the trench depth of the isolation region; and an N + pickup in the memory N well, also includes a floating gate extension that extends continuously from the floating gate to the second OD region. This extension is located next to an erase gate (EG) region within the second OD region.
9. The NVM cell according to claim 8 , wherein the floating gate extension traverses the isolation region between the first OD region and the second OD region and partially overlaps with the second OD region to capacitively couple to the EG region.
The nonvolatile memory (NVM) cell, which includes a floating gate extension continuously extended from the floating gate to the second OD region and is adjacent to an erase gate (EG) region in the second OD region (part of a cell including a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the OD regions, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor disposed on the first OD region with a floating gate overlying the region; a memory P well in the substrate overlapping both OD regions, with a junction depth greater than the trench depth and a continuous well structure between the OD regions; a memory N well in the P well only overlapping the first OD region, with a junction depth less than the trench depth; and an N + pickup in the N well) has its floating gate extension crossing the isolation region between the two OD regions and partially overlapping the second OD region. This overlap creates capacitive coupling to the EG region.
10. The NVM cell according to claim 8 , wherein the EG region comprises a double diffused drain (DDD) region and an N + doping region in the DDD region.
The nonvolatile memory (NVM) cell, which includes a floating gate extension continuously extended from the floating gate to the second OD region and is adjacent to an erase gate (EG) region in the second OD region (part of a cell including a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the OD regions, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor disposed on the first OD region with a floating gate overlying the region; a memory P well in the substrate overlapping both OD regions, with a junction depth greater than the trench depth and a continuous well structure between the OD regions; a memory N well in the P well only overlapping the first OD region, with a junction depth less than the trench depth; and an N + pickup in the N well) forms its EG region using a double diffused drain (DDD) region containing an N+ doping region.
11. The NVM cell according to claim 10 , wherein the DDD region is an N-type doping region.
The nonvolatile memory (NVM) cell, which includes an erase gate (EG) region comprising a double diffused drain (DDD) region and an N + doping region in the DDD region (part of a cell including a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the OD regions, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor disposed on the first OD region with a floating gate overlying the region; a memory P well in the substrate overlapping both OD regions, with a junction depth greater than the trench depth and a continuous well structure between the OD regions; a memory N well in the P well only overlapping the first OD region, with a junction depth less than the trench depth; and an N + pickup in the N well, as well as a floating gate extension continuously extended from the floating gate to the second OD region and is adjacent to the erase gate (EG) region in the second OD region) has its DDD region as an N-type doping region.
12. The NVM cell according to claim 10 , wherein the N + doping region and the DDD region are electrically coupled to an erase line voltage (V EL ).
The nonvolatile memory (NVM) cell, which includes an erase gate (EG) region comprising a double diffused drain (DDD) region and an N + doping region in the DDD region (part of a cell including a semiconductor substrate; a first OD region and a second OD region; an isolation region separating the OD regions, the isolation region having a trench depth; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor disposed on the first OD region with a floating gate overlying the region; a memory P well in the substrate overlapping both OD regions, with a junction depth greater than the trench depth and a continuous well structure between the OD regions; a memory N well in the P well only overlapping the first OD region, with a junction depth less than the trench depth; and an N + pickup in the N well, as well as a floating gate extension continuously extended from the floating gate to the second OD region and is adjacent to the erase gate (EG) region in the second OD region) connects both the N+ doping region and the DDD region within the EG region to an erase line voltage (V_EL).
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May 22, 2015
May 2, 2017
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