Patentable/Patents/US-9640497
US-9640497

Semiconductor backmetal (BM) and over pad metallization (OPM) structures and related methods

PublishedMay 2, 2017
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

Patent Claims
15 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 1

Original Legal Text

1. A method of forming a plurality of semiconductor devices, comprising: providing a semiconductor wafer having a first side and a second side opposite the first side, one or more electrically conductive pads coupled at the second side, and one or more electrically insulative layers coupled at the second side and having one or more openings providing access to the one or more electrically conductive pads; backgrinding the first side of the wafer to a desired thickness; depositing an electrically conductive layer on the first side of the wafer; simultaneously electrolessly depositing a first nickel layer over the electrically conductive layer and a second nickel layer over the one or more electrically conductive pads, and; simultaneously depositing a first diffusion barrier layer over the first nickel layer and a second diffusion barrier layer over the second nickel layer.

Plain English Translation

A method for manufacturing semiconductor devices involves starting with a semiconductor wafer that has two sides. One side has electrical contact pads and insulating layers with openings to expose these pads. The opposite side of the wafer is ground down to the required thickness. Then, a conductive layer is deposited on the ground side. Next, a nickel layer is simultaneously applied without using electricity (electrolessly) to both the conductive layer on the ground side and to the electrical contact pads on the other side. Finally, diffusion barrier layers are also simultaneously deposited on top of each of the nickel layers. This creates a backmetal structure on one side and over pad metallization on the other.

Claim 2

Original Legal Text

2. The method of claim 1 , wherein backgrinding the first side of the wafer comprises forming a substantially circular recess in the first side of the wafer bounded by a ring of non-removed material.

Plain English Translation

The semiconductor device manufacturing method from the previous description includes a step where the backgrinding process on the first side of the wafer creates a shallow, circular depression. This depression doesn't go all the way to the edge; instead, a ring of the original wafer material is left around the perimeter of the ground-down area. This ring provides structural support or allows for easier handling during subsequent processing steps.

Claim 3

Original Legal Text

3. The method of claim 1 , wherein the first diffusion barrier layer and the second diffusion barrier layer each comprises one of electrolessly deposited gold and electrolessly deposited silver.

Plain English Translation

In the semiconductor device manufacturing method, the diffusion barrier layers used on both the backmetal and over pad metallization sides are made of either gold or silver, applied using an electroless deposition process. Electroless deposition is used to ensure uniform coating thickness and conformal coverage of the underlying nickel layers, enhancing the barrier properties of gold or silver against diffusion of metal atoms.

Claim 4

Original Legal Text

4. The method of claim 1 , wherein the first diffusion barrier layer and the second diffusion barrier layer each comprises an organic solderability preservative (OSP).

Plain English Translation

In the semiconductor device manufacturing method, the diffusion barrier layers used on both the backmetal and over pad metallization sides consist of an Organic Solderability Preservative (OSP). An OSP coating protects the underlying nickel from oxidation and enhances solderability during the device packaging process. The OSP layer provides a clean surface for solder attachment, ensuring good electrical contact and long-term reliability.

Claim 5

Original Legal Text

5. The method of claim 1 , wherein the one or more electrically insulative layers comprises polyimide.

Plain English Translation

In the semiconductor device manufacturing method, the insulating layers on the second side of the semiconductor wafer, which cover the electrical contact pads but have openings to expose them, are made of polyimide. Polyimide provides electrical insulation and mechanical protection for the underlying circuitry and acts as a dielectric material between conductive elements.

Claim 6

Original Legal Text

6. The method of claim 1 , further comprising introducing dopants into the wafer through the first side of the wafer and annealing the wafer.

Plain English Translation

The semiconductor device manufacturing method further includes introducing dopant atoms into the wafer through the first, ground-down side and then heating the wafer in an annealing process. Doping modifies the electrical properties of the semiconductor material, creating regions with controlled conductivity. Annealing activates the dopants, allowing them to diffuse into the silicon lattice and form the desired electrical junctions within the semiconductor device.

Claim 7

Original Legal Text

7. The method of claim 1 , wherein the electrically conductive layer comprises AlCu.

Plain English Translation

In the semiconductor device manufacturing method, the electrically conductive layer deposited on the ground side of the wafer (prior to nickel deposition) is made of an aluminum-copper alloy (AlCu). The AlCu layer provides a conductive base for the backmetal stack and facilitates electrical connection to the semiconductor device.

Claim 8

Original Legal Text

8. The method of claim 1 , further comprising forming one of a plurality of insulated gate bipolar transistors (IGBTs) and a plurality of diodes on the wafer.

Plain English Translation

The semiconductor device manufacturing method further includes fabricating either insulated gate bipolar transistors (IGBTs) or diodes on the semiconductor wafer. These devices are manufactured using standard semiconductor processing techniques like photolithography, etching, and deposition. The subsequent backmetal and over pad metallization steps provide electrical connections to these components.

Claim 9

Original Legal Text

9. A method of forming a plurality of semiconductor devices, comprising: providing a semiconductor wafer having a first side and a second side opposite the first side, one or more electrically conductive pads coupled at the second side, and one or more electrically insulative layers coupled at the second side and having one or more openings providing access to the one or more electrically conductive pads; backgrinding the first side of the wafer to a desired thickness; depositing an electrically conductive layer on the first side of the wafer; depositing one or more backmetal (BM) layers on the electrically conductive layer, the one or more BM layers comprising one of a titanium layer, a nickel layer, and a silver layer; covering the one or more BM layers with a protective coating; electrolessly depositing a nickel layer over the one or more electrically conductive pads; depositing a diffusion barrier layer over the nickel layer, and; removing the protective coating from the one or more BM layers.

Plain English Translation

A method for manufacturing semiconductor devices involves starting with a wafer, grinding one side, depositing a conductive layer on that side, and then depositing one or more backmetal (BM) layers on the conductive layer. These BM layers consist of titanium, nickel, or silver. A protective coating is then applied over the BM layers. Separately, a nickel layer is electrolessly deposited over the electrical contact pads on the other side of the wafer, followed by a diffusion barrier layer. Finally, the protective coating is removed from the BM layers, completing the electrical connection on both sides of the die.

Claim 10

Original Legal Text

10. The method of claim 9 , wherein the one or more BM layers comprises a titanium layer, a nickel layer, and a silver layer.

Plain English Translation

In the semiconductor device manufacturing method described previously, the backmetal (BM) layers deposited on the conductive layer consist of a stack of three metals: a titanium layer, a nickel layer, and a silver layer. Titanium promotes adhesion to the underlying conductive layer. Nickel provides a diffusion barrier, and silver provides a highly conductive top layer for solder attachment.

Claim 11

Original Legal Text

11. The method of claim 9 , wherein the diffusion barrier layer comprises one of electrolessly deposited gold, electrolessly deposited silver, and an organic solderability preservative (OSP).

Plain English Translation

In the semiconductor device manufacturing method described previously, the diffusion barrier layer deposited over the nickel layer on the electrical contact pads is made of electrolessly deposited gold, electrolessly deposited silver, or an Organic Solderability Preservative (OSP). These materials prevent diffusion and oxidation of the underlying nickel layer, enhancing the reliability of the electrical connection to the pads.

Claim 12

Original Legal Text

12. The method of claim 9 , further comprising introducing dopants into the wafer through the first side of the wafer.

Plain English Translation

The semiconductor device manufacturing method described previously further includes introducing dopant atoms into the wafer through the ground-down side. Doping modifies the electrical properties of the semiconductor material, creating regions with controlled conductivity for the semiconductor devices being manufactured.

Claim 13

Original Legal Text

13. The method of claim 9 , wherein the electrically conductive layer comprises evaporated aluminum.

Plain English Translation

In the semiconductor device manufacturing method, the electrically conductive layer deposited on the ground side of the wafer, before the backmetal layers, is made of evaporated aluminum. Evaporated aluminum forms a conductive base layer for the subsequent backmetal stack, improving overall electrical performance and reliability.

Claim 14

Original Legal Text

14. The method of claim 9 , wherein the protective coating comprises an adhesive tape.

Plain English Translation

In the semiconductor device manufacturing method, the protective coating applied over the backmetal (BM) layers is an adhesive tape. This tape protects the BM layers during subsequent processing steps, such as dicing or handling, preventing damage or contamination of the metallized surface.

Claim 15

Original Legal Text

15. The method of claim 9 , further comprising depositing the one or more BM layers through evaporation.

Plain English Translation

The semiconductor device manufacturing method includes a step where the backmetal (BM) layers are deposited using evaporation. This technique provides precise control over layer thickness and composition, ensuring optimal electrical and mechanical properties of the backmetal stack.

Classification Codes (CPC)

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Patent Metadata

Filing Date

June 30, 2016

Publication Date

May 2, 2017

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