Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A circuit comprising: a static random access memory (SRAM); a second memory; and processing circuitry operable to: periodically invert data within the SRAM and concurrently invert data within the second memory; perform a logical exclusive-OR operation between a data output signal of the SRAM and a data output signal of the second memory; and selection circuitry for using a first signal to select between a second signal and a complemented data output signal of the SRAM as a selection circuit output signal.
A circuit designed to prevent data remanence includes a static random access memory (SRAM) for storing data, and a second memory. Processing circuitry periodically inverts the data in both the SRAM and the second memory simultaneously. This circuit performs an exclusive-OR (XOR) operation between the data output from the SRAM and the data output from the second memory. Finally, selection circuitry uses a signal to choose between a secondary signal or the complemented (inverted) data output from the SRAM, producing a selection circuit output signal.
2. The circuit of claim 1 , wherein the processing circuitry is further operable to: write data to the SRAM, and reset the second memory.
In addition to the components from the previous description, the data remanence prevention circuit's processing circuitry also writes data to the SRAM and resets the second memory. The SRAM is where the primary data is stored, while the second memory helps track the inversion state, allowing the original data to be reconstructed even after periodic inversions. Resetting the second memory ensures a consistent starting point for tracking inversions when new data is written to the SRAM.
3. The circuit of claim 1 , wherein at least a part of a combination of the second memory and the processing circuitry is located within the SRAM.
In the data remanence prevention circuit, at least a portion of the combination of the second memory and the processing circuitry resides within the SRAM itself. This means that some or all of the logic that handles the data inversion tracking and the XOR operation could be physically integrated into the SRAM chip, rather than existing as separate external components.
4. The circuit of claim 1 , wherein the second memory and the processing circuitry are located outside the SRAM.
Conversely to the previous configuration, the data remanence prevention circuit can also be designed so that the second memory and the processing circuitry are located outside of the SRAM. This means that the logic handling data inversion tracking and the XOR operation are implemented using components external to the SRAM chip.
5. The circuit of claim 1 , wherein a rate at which the processing circuitry is operable to periodically invert data within the SRAM concurrently with data within the second memory is configurable.
The rate at which the processing circuitry in the data remanence prevention circuit inverts data within the SRAM and the second memory is configurable. This means the frequency of data inversion can be adjusted based on factors like security requirements, performance needs, or power consumption considerations. The system can adapt the inversion rate to optimize data protection against remanence while balancing other system constraints.
6. The circuit of claim 1 , wherein: the SRAM comprises a plurality of memory cells each containing only one data bit, and the second memory comprises a register containing only one data bit.
The SRAM within the data remanence prevention circuit consists of multiple memory cells, each storing a single bit of data. The second memory, responsible for tracking the inversion state, consists of a register that contains only one data bit. This indicates a bit-by-bit inversion tracking mechanism, likely used when a single bit or small number of bits are stored.
7. The circuit of claim 1 , wherein the SRAM is operable to store a cryptographic key.
The SRAM in the data remanence prevention circuit is specifically used to store a cryptographic key. This implies the circuit is designed to protect sensitive cryptographic keys from data remanence attacks by periodically inverting the key and using the second memory to track the inversion state for reconstruction.
8. A field-programmable gate array (FPGA) containing the circuit as defined in claim 1 , wherein the SRAM is operable to store a cryptographic key, and wherein the cryptographic key is used by the FPGA to store and communicate data.
A field-programmable gate array (FPGA) incorporates the data remanence prevention circuit described previously. In this FPGA, the SRAM is used to store a cryptographic key. This key is then used by the FPGA for secure data storage and communication. This highlights a practical application of the data remanence circuit in protecting cryptographic keys within an FPGA environment.
9. A circuit comprising: a first memory; a second memory; exclusive-OR circuitry for providing an exclusive-OR circuit output signal, wherein the exclusive-OR circuit output signal is a logical exclusive-OR function of a data output signal of the first memory and a data output signal of the second memory; selection circuitry for using a first signal to select a second signal or a complemented data output signal of the first memory as a selection circuit output signal; and interconnection circuitry configurable to: couple a complemented data output signal of the second memory to a data input signal of the second memory; couple the first signal to a reset signal of the second memory, and couple the selection circuit output signal to a data input signal of the first memory.
A circuit prevents data remanence using a first memory, a second memory, and an XOR circuit. The XOR circuit outputs the result of an XOR operation between the data from the first and second memories. Selection circuitry chooses between a secondary signal and the inverted output of the first memory. Configurable interconnection circuitry connects the inverted output of the second memory to its input, connects a first signal to the reset of the second memory, and connects the output of the selection circuit to the input of the first memory.
10. The circuit of claim 9 , further comprising clock circuitry and additional interconnection circuitry configured to: couple a clock circuitry output signal to a clock input signal of the first memory, and couple the clock circuitry output signal to a clock input signal of the second memory.
Building upon the previous data remanence prevention circuit description, this version adds clock circuitry and additional configurable interconnection circuitry. This circuitry connects the output of the clock to the clock input of both the first and second memories, ensuring synchronous operation and data inversion. The clock circuitry provides the timing signal for the memory operations, ensuring coordinated data manipulation in both memories.
11. The circuit of claim 9 , wherein: the first memory comprises a plurality of memory cells each containing one data bit, and the second memory comprises a register containing one data bit.
In the data remanence prevention circuit, the first memory is comprised of memory cells that each hold a single data bit. The second memory is a register that also holds only one data bit. This reinforces the concept of bit-level tracking of the data inversion state to prevent remanence effects.
12. The circuit of claim 9 , wherein the first memory comprises static random access memory (SRAM).
The first memory in the data remanence prevention circuit is a static random access memory (SRAM). This specifies the type of memory being protected from data remanence, indicating its suitability for applications needing high speed and frequent access.
13. The circuit of claim 9 , wherein the selection circuitry comprises a multiplexer.
The selection circuitry in the data remanence prevention circuit is implemented using a multiplexer. This clarifies how the circuit chooses between the original data and the complemented data output, likely controlled by the inversion state tracking mechanism.
14. The circuit of claim 9 , further comprising: first level shifter circuitry, wherein the interconnection circuitry is further configurable to: couple a first level shifter circuitry output signal to the second signal; and second level shifter circuitry, wherein the interconnection circuitry is further configurable to: couple a second level shifter circuitry input signal to a load signal, and couple a second level shifter circuitry output signal to the first signal.
Expanding on the data remanence prevention circuit design, first and second level shifter circuits are added. The configurable interconnection circuitry now connects the output of the first level shifter to a secondary signal. It also connects the input of the second level shifter to a load signal and the output of the second level shifter to the control signal used by the selection circuitry. These level shifters likely handle voltage domain transitions between different circuit parts.
15. The circuit of claim 9 , wherein the first memory is used for storing a cryptographic key.
The first memory within the data remanence prevention circuit is specifically utilized to store a cryptographic key. This emphasizes the application of the circuit in protecting sensitive cryptographic data from being recovered through remanence analysis.
16. A field-programmable gate array (FPGA) containing the circuit as in claim 9 .
A field-programmable gate array (FPGA) contains the data remanence prevention circuit. This puts the prior described circuit in a real application, and shows how its value in preventing data leaks on systems commonly used.
17. The FPGA of claim 16 , wherein: the first memory stores a cryptographic key, and the cryptographic key is used by the FPGA to store and communicate data.
In this FPGA containing the data remanence prevention circuit, the first memory stores a cryptographic key. This cryptographic key is used by the FPGA for storing and communicating data securely. This shows a use-case for the system in a common computing application.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 29, 2011
May 9, 2017
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