Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
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1. A semiconductor structure, comprising: an NMOS transistor and a PMOS transistor above a silicon substrate; a first gate stack for the PMOS transistor, the first gate stack comprising a workfunction metal layer; a second gate stack for the NMOS transistor, the second gate stack comprising a layer comprising titanium and aluminum, wherein the workfunction metal layer of the first gate stack is not included in the second gate stack, and wherein the layer comprising titanium and aluminum is over the workfunction metal layer in the first gate stack; a source region and a drain region for the NMOS transistor; a raised source region and a raised drain region for the PMOS transistor, the raised source and drain regions comprising a silicon germanium layer creating a stressed channel for the PMOS device, and the raised source and drain regions extending above a surface of the silicon substrate over which the first gate stack is formed; and a nitride layer over the silicon germanium layer and co-planar with an uppermost surface of the first gate stack.
This semiconductor structure enhances transistor strain and comprises an NMOS transistor and a PMOS transistor positioned above a silicon substrate. The PMOS transistor uses a first gate stack including a workfunction metal layer. The NMOS transistor uses a second gate stack including a titanium and aluminum layer. The workfunction metal layer from the PMOS gate stack is not in the NMOS gate stack, and the titanium/aluminum layer is above the workfunction metal layer in the PMOS gate stack. The NMOS transistor has a source and drain region. The PMOS transistor has raised source and drain regions composed of silicon germanium, creating a stressed channel. These raised regions extend above the silicon substrate's surface where the PMOS gate stack sits. A nitride layer covers the silicon germanium and is level with the top of the PMOS gate stack.
2. The semiconductor structure of claim 1 , wherein the first and second gate stacks comprise a same fill metal.
The semiconductor structure, which enhances transistor strain and comprises an NMOS transistor and a PMOS transistor positioned above a silicon substrate, utilizes a specific gate configuration. The PMOS transistor uses a first gate stack including a workfunction metal layer, while the NMOS transistor uses a second gate stack including a titanium and aluminum layer. The workfunction metal layer from the PMOS gate stack is not in the NMOS gate stack, and the titanium/aluminum layer is above the workfunction metal layer in the PMOS gate stack. The NMOS transistor has a source and drain region. The PMOS transistor has raised source and drain regions of silicon germanium, creating a stressed channel. These raised regions extend above the silicon substrate's surface where the PMOS gate stack sits. A nitride layer covers the silicon germanium and is level with the top of the PMOS gate stack. Both the first and second gate stacks use the same fill metal.
3. The semiconductor structure of claim 1 , wherein the first and second gate stacks comprise a first and second gate dielectric layer, respectively.
The semiconductor structure, which enhances transistor strain and comprises an NMOS transistor and a PMOS transistor positioned above a silicon substrate, utilizes a specific gate configuration. The PMOS transistor uses a first gate stack including a workfunction metal layer, while the NMOS transistor uses a second gate stack including a titanium and aluminum layer. The workfunction metal layer from the PMOS gate stack is not in the NMOS gate stack, and the titanium/aluminum layer is above the workfunction metal layer in the PMOS gate stack. The NMOS transistor has a source and drain region. The PMOS transistor has raised source and drain regions of silicon germanium, creating a stressed channel. These raised regions extend above the silicon substrate's surface where the PMOS gate stack sits. A nitride layer covers the silicon germanium and is level with the top of the PMOS gate stack. The first and second gate stacks include a first and second gate dielectric layer, respectively.
4. The semiconductor structure of claim 3 , wherein the first and second gate dielectric layers comprise U-shaped gate dielectric layers.
The semiconductor structure utilizes an NMOS and PMOS transistor above a silicon substrate to enhance transistor strain. The PMOS transistor uses a first gate stack including a workfunction metal layer, while the NMOS transistor uses a second gate stack including a titanium and aluminum layer. The workfunction metal layer from the PMOS gate stack is absent from the NMOS gate stack, and the titanium/aluminum layer sits above the workfunction metal layer in the PMOS gate stack. The NMOS transistor has a source and drain region. The PMOS transistor has raised source and drain regions of silicon germanium, creating a stressed channel, extending above the silicon substrate where the PMOS gate stack is formed. A nitride layer covers the silicon germanium and is level with the top of the PMOS gate stack. Both the first and second gate stacks include a first and second gate dielectric layer, respectively, and these gate dielectric layers have a U-shaped configuration.
5. The semiconductor structure of claim 3 , wherein the first and second gate dielectric layers comprise hafnium oxide.
The semiconductor structure utilizes an NMOS and PMOS transistor above a silicon substrate to enhance transistor strain. The PMOS transistor uses a first gate stack including a workfunction metal layer, while the NMOS transistor uses a second gate stack including a titanium and aluminum layer. The workfunction metal layer from the PMOS gate stack is absent from the NMOS gate stack, and the titanium/aluminum layer sits above the workfunction metal layer in the PMOS gate stack. The NMOS transistor has a source and drain region. The PMOS transistor has raised source and drain regions of silicon germanium, creating a stressed channel, extending above the silicon substrate where the PMOS gate stack is formed. A nitride layer covers the silicon germanium and is level with the top of the PMOS gate stack. Both the first and second gate stacks include a first and second gate dielectric layer, respectively, and these gate dielectric layers comprise hafnium oxide.
6. The semiconductor structure of claim 1 , further comprising a silicide layer on the silicon germanium layer.
The semiconductor structure enhances transistor strain and comprises an NMOS transistor and a PMOS transistor positioned above a silicon substrate. The PMOS transistor uses a first gate stack including a workfunction metal layer, while the NMOS transistor uses a second gate stack including a titanium and aluminum layer. The workfunction metal layer from the PMOS gate stack is not in the NMOS gate stack, and the titanium/aluminum layer is above the workfunction metal layer in the PMOS gate stack. The NMOS transistor has a source and drain region. The PMOS transistor has raised source and drain regions of silicon germanium, creating a stressed channel. These raised regions extend above the silicon substrate's surface where the PMOS gate stack sits. A nitride layer covers the silicon germanium and is level with the top of the PMOS gate stack. A silicide layer is added on top of the silicon germanium layer.
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April 28, 2016
May 9, 2017
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