A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.
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1. A method of fabricating a diode in a device area on a semiconductor substrate, the method comprising: forming an isolation region disposed at a surface of the semiconductor substrate; performing a first dopant implantation procedure to form a first well region disposed in the semiconductor substrate, wherein the first well region has a first conductivity type, and the first well region includes a portion of the first well region that extends to the surface of the semiconductor substrate; performing a second dopant implantation procedure to form a buried region disposed in the semiconductor substrate, wherein the buried region has the first conductivity type; performing a third dopant implantation procedure to form a first contact region disposed at the surface of the semiconductor substrate, wherein the first contact region has the first conductivity type, and the first, second, and third dopant implantation procedures are configured such that the buried region is electrically connected with the first contact region; and performing a fourth dopant implantation procedure to form a second contact region disposed at the surface of the semiconductor substrate, wherein the second contact region has a second conductivity type, the second contact region is vertically adjacent to the buried region, the isolation region is laterally disposed between the second contact region and the first contact region, and the portion of the first well region forms a separation region that is laterally disposed between the second contact region and the isolation region.
A method for building a diode on a semiconductor substrate involves these steps: First, create an isolation region on the substrate's surface. Next, implant dopants to form a first well region within the substrate, ensuring a portion of this well reaches the surface. Then, perform another dopant implantation to create a buried region within the substrate, with the same conductivity type as the first well. After that, implant dopants to form a first contact region on the substrate's surface, also having the same conductivity type. Crucially, these implantations ensure the buried region is electrically connected to the first contact region. Finally, implant dopants to form a second contact region on the surface, but with an opposite conductivity type. This second contact is vertically near the buried region. The isolation region sits laterally between the two contact regions, and a separation region formed by the first well, separates the first contact region and isolation region.
2. The method of claim 1 , further comprising: performing a fifth dopant implantation procedure to form an intermediate region disposed at the surface of the semiconductor substrate, wherein the intermediate region has the second conductivity type, and the fourth and fifth dopant implantation procedures are configured such that: the intermediate region is laterally adjacent to the second contact region, and the intermediate region is electrically connected with the second contact region.
The diode fabrication method described previously (forming an isolation region, first well region, buried region, first contact region, and second contact region) also includes an additional step: implanting dopants to create an intermediate region on the substrate's surface. This intermediate region has the same conductivity type as the second contact region. The implantation process is designed so that the intermediate region sits laterally next to the second contact region and is electrically connected to it. This creates a more complex diode structure.
3. The method of claim 2 , wherein the intermediate region is further laterally adjacent to the separation region, and a lateral junction is established at an interface between a lateral edge of the intermediate region and the separation region.
In the diode fabrication method with the added intermediate region (forming an isolation region, first well region, buried region, first contact region, second contact region, and intermediate region), the intermediate region is also laterally adjacent to the separation region. This creates a lateral junction at the interface where the intermediate region's edge meets the separation region. This junction affects the diode's electrical characteristics.
4. The method of claim 1 , wherein the performing the first dopant implantation procedure further forms a centered well region disposed in the semiconductor substrate centered within the device area, wherein the centered well region is vertically adjacent to the buried region, the buried region is also centered within the device area, the centered well region extends laterally across at least a portion of the buried region, and the first well region is laterally adjacent to the centered well region.
The diode fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region) includes forming a centered well region within the substrate. This region sits vertically near the buried region, which is also centered. The centered well extends across at least part of the buried region and is laterally adjacent to the first well region, adding complexity to the diode's structure and electrical behavior.
5. The method of claim 1 , further comprising: depositing a silicide block on the surface of the semiconductor substrate over the separation region.
The diode fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region) incorporates a silicide block deposited on the substrate's surface directly over the separation region. This silicide block serves to prevent silicide formation in that specific area, influencing the diode's contact resistance and overall performance.
6. The method of claim 1 , wherein an inner vertical junction is established at an interface between the second contact region and the buried region.
In the diode fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region), an inner vertical junction is formed at the interface between the second contact region and the buried region. This junction plays a crucial role in the diode's operation and electrical characteristics.
7. The method of claim 1 , wherein a lateral junction is established at an interface between a lateral edge of the second contact region and the separation region.
In the diode fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region), a lateral junction is formed at the interface between the second contact region's lateral edge and the separation region. This lateral junction influences the diode's electrical behavior, particularly its breakdown voltage and leakage current.
8. The method of claim 1 , wherein the second contact region is centered over the first well region, the second contact region extends laterally across at least a portion of the first well region, and a vertical junction is established at an interface between the second contact region and the first well region.
In the diode fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region), the second contact region is centered above the first well region and extends across at least a portion of it. This configuration results in a vertical junction at the interface between the second contact region and the first well region, affecting the diode's electrical characteristics.
9. The method of claim 4 , wherein at least a portion of the second contact region extends laterally across the centered well region, and a vertical junction is established at an interface between the second contact region and the centered well region.
In the diode fabrication method that forms a centered well region (forming an isolation region, first well region, buried region, first contact region, second contact region, and centered well region), at least a portion of the second contact region extends laterally across the centered well region. This overlap creates a vertical junction at the interface between the second contact region and the centered well region, influencing the diode's electrical behavior.
10. The method of claim 4 , further comprising: performing a fifth dopant implantation procedure to form an intermediate region disposed at the surface of the semiconductor substrate, wherein the first and fifth dopant implantation procedures are configured such that: at least a portion of the intermediate region extends laterally across the centered well region, and a vertical junction is established at an interface between the intermediate region and the centered well region.
The diode fabrication method including the centered well (forming an isolation region, first well region, buried region, first contact region, second contact region, and centered well region) further involves forming an intermediate region on the substrate's surface. The implantation process is configured so that at least a portion of this intermediate region extends laterally across the centered well region. This results in a vertical junction at the interface between the intermediate region and the centered well region, impacting the diode's functionality.
11. The method of claim 1 , wherein the performing the first dopant implantation procedure further forms a second well region disposed in the semiconductor substrate under at least a portion of the isolation region and laterally adjacent to the first well region, wherein the second well region has the first conductivity type, the first and third dopant implantation procedures are configured such that the second well region is electrically connected to the first contact region, and the second well region has a higher dopant concentration than the first well region.
The diode fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region) includes forming a second well region under at least a portion of the isolation region and laterally adjacent to the first well region. This second well has the same conductivity type as the first well region, is electrically connected to the first contact region, and has a higher dopant concentration than the first well region. This modifies the electric field distribution and behavior of the diode.
12. The method of claim 11 , wherein the performing the first dopant implantation procedure further forms a third well region disposed in the semiconductor substrate laterally adjacent to the second well region, wherein the third well region has the first conductivity type, the first and third dopant implantation procedures are further configured such that the third well region is electrically connected to the first contact region, and the third well region has a higher dopant concentration than the second well region.
The diode fabrication method including the second well region (forming an isolation region, first well region, buried region, first contact region, second contact region, and second well region) further forms a third well region laterally adjacent to the second well region. This third well region also has the same conductivity type and is electrically connected to the first contact region, but its dopant concentration is higher than that of the second well region. This creates a dopant concentration gradient for tailoring the diode characteristics.
13. The method of claim 1 , wherein the performing the first dopant implantation procedure further forms an outer well region disposed in the semiconductor substrate under at least a portion of the first contact region and laterally adjacent to the first well region, wherein the outer well region has the first conductivity type, the first and third dopant implantation procedures are further configured such that the outer well region is electrically connected to the first contact region, and the outer well region has a higher dopant concentration than the first well region.
The diode fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region) includes forming an outer well region under at least a portion of the first contact region and laterally adjacent to the first well region. This outer well region has the same conductivity type and is electrically connected to the first contact region, but its dopant concentration is higher than the first well region. This alters the contact resistance and the behavior of the diode near the contact.
14. The method of claim 1 , wherein the isolation region comprises a shallow trench isolation (STI) region.
In the diode fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region), the isolation region is specifically a shallow trench isolation (STI) region. An STI region is created by etching a shallow trench into the silicon and filling it with an insulating material, like silicon dioxide, to isolate different device components.
15. The method of claim 1 , wherein the diode comprises one of a group including a Zener diode and a low voltage diode.
The diode created by the described fabrication method (forming an isolation region, first well region, buried region, first contact region, and second contact region) is either a Zener diode or a low voltage diode. Zener diodes are designed to operate in reverse breakdown mode at a specific voltage, while low voltage diodes are optimized for applications requiring forward conduction at low voltage levels.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 30, 2016
May 9, 2017
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