A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a diode in a device area on a semiconductor substrate, the method comprising: forming an isolation region disposed at a surface of the semiconductor substrate; performing a first dopant implantation procedure to form a first well region disposed in the semiconductor substrate, wherein the first well region has a first conductivity type, and the first well region includes a portion of the first well region that extends to the surface of the semiconductor substrate; performing a second dopant implantation procedure to form a buried region disposed in the semiconductor substrate, wherein the buried region has the first conductivity type; performing a third dopant implantation procedure to form a first contact region disposed at the surface of the semiconductor substrate, wherein the first contact region has the first conductivity type, and the first, second, and third dopant implantation procedures are configured such that the buried region is electrically connected with the first contact region; and performing a fourth dopant implantation procedure to form a second contact region disposed at the surface of the semiconductor substrate, wherein the second contact region has a second conductivity type, the second contact region is vertically adjacent to the buried region, the isolation region is laterally disposed between the second contact region and the first contact region, and the portion of the first well region forms a separation region that is laterally disposed between the second contact region and the isolation region.
2. The method of claim 1 , further comprising: performing a fifth dopant implantation procedure to form an intermediate region disposed at the surface of the semiconductor substrate, wherein the intermediate region has the second conductivity type, and the fourth and fifth dopant implantation procedures are configured such that: the intermediate region is laterally adjacent to the second contact region, and the intermediate region is electrically connected with the second contact region.
3. The method of claim 2 , wherein the intermediate region is further laterally adjacent to the separation region, and a lateral junction is established at an interface between a lateral edge of the intermediate region and the separation region.
4. The method of claim 1 , wherein the performing the first dopant implantation procedure further forms a centered well region disposed in the semiconductor substrate centered within the device area, wherein the centered well region is vertically adjacent to the buried region, the buried region is also centered within the device area, the centered well region extends laterally across at least a portion of the buried region, and the first well region is laterally adjacent to the centered well region.
5. The method of claim 1 , further comprising: depositing a silicide block on the surface of the semiconductor substrate over the separation region.
6. The method of claim 1 , wherein an inner vertical junction is established at an interface between the second contact region and the buried region.
7. The method of claim 1 , wherein a lateral junction is established at an interface between a lateral edge of the second contact region and the separation region.
8. The method of claim 1 , wherein the second contact region is centered over the first well region, the second contact region extends laterally across at least a portion of the first well region, and a vertical junction is established at an interface between the second contact region and the first well region.
9. The method of claim 4 , wherein at least a portion of the second contact region extends laterally across the centered well region, and a vertical junction is established at an interface between the second contact region and the centered well region.
10. The method of claim 4 , further comprising: performing a fifth dopant implantation procedure to form an intermediate region disposed at the surface of the semiconductor substrate, wherein the first and fifth dopant implantation procedures are configured such that: at least a portion of the intermediate region extends laterally across the centered well region, and a vertical junction is established at an interface between the intermediate region and the centered well region.
11. The method of claim 1 , wherein the performing the first dopant implantation procedure further forms a second well region disposed in the semiconductor substrate under at least a portion of the isolation region and laterally adjacent to the first well region, wherein the second well region has the first conductivity type, the first and third dopant implantation procedures are configured such that the second well region is electrically connected to the first contact region, and the second well region has a higher dopant concentration than the first well region.
12. The method of claim 11 , wherein the performing the first dopant implantation procedure further forms a third well region disposed in the semiconductor substrate laterally adjacent to the second well region, wherein the third well region has the first conductivity type, the first and third dopant implantation procedures are further configured such that the third well region is electrically connected to the first contact region, and the third well region has a higher dopant concentration than the second well region.
13. The method of claim 1 , wherein the performing the first dopant implantation procedure further forms an outer well region disposed in the semiconductor substrate under at least a portion of the first contact region and laterally adjacent to the first well region, wherein the outer well region has the first conductivity type, the first and third dopant implantation procedures are further configured such that the outer well region is electrically connected to the first contact region, and the outer well region has a higher dopant concentration than the first well region.
14. The method of claim 1 , wherein the isolation region comprises a shallow trench isolation (STI) region.
15. The method of claim 1 , wherein the diode comprises one of a group including a Zener diode and a low voltage diode.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 30, 2016
May 9, 2017
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