Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.
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1. A portable electronic device having a Global Navigation Satellite System (GNSS) receiver, comprising: a GNSS oscillator configured to output a GNSS timing signal for the GNSS receiver; a Real Time Clock (RTC) oscillator configured to output an RTC timing signal; a resistance/capacitance (RC) oscillator configured to output a digital pulse signal; and a digital RTC monitor Integrated Circuit (IC) configured to monitor the RTC oscillator timing signal, the digital RTC Monitor IC comprising: an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles, wherein the GNSS receiver, when re-starting GNSS operations after the GNSS oscillator has been powered down, does not use the RTC timing signal to re-correlate GNSS operations when the RTC reset signal has been asserted.
A portable electronic device with a GNSS receiver uses a digital Real Time Clock (RTC) monitor Integrated Circuit (IC) to check the RTC oscillator. The GNSS receiver relies on a GNSS oscillator for timing. The RTC oscillator provides a separate timing signal. An RC oscillator outputs digital pulses. The RTC monitor IC watches the RTC oscillator's timing using the RC oscillator's pulses. If the RTC oscillator misses clock cycles compared to the RC oscillator, the IC sends an RTC reset signal. After the GNSS oscillator powers back on, the GNSS receiver will not use the potentially faulty RTC timing if the RTC reset signal was triggered.
2. The portable electronic device of claim 1 , wherein a frequency of the RC oscillator input signal is divided before the digital RTC monitor IC compares it with the RTC input.
In the portable electronic device using the digital Real Time Clock (RTC) monitor Integrated Circuit (IC) as described in claim 1, the frequency of the digital pulse signal from the RC oscillator is reduced via frequency division before being compared to the RTC oscillator signal inside the RTC monitor IC. This allows the IC to monitor the RTC oscillator over a longer period of time, increasing the accuracy of the fault detection. The RTC oscillator is checked against this divided RC oscillator signal.
3. The portable electronic device of claim 1 , wherein the digital IC further comprises: a latch configured to receive the RTC reset signal and to assert an RTC monitor signal when the RTC reset signal is asserted, wherein the RTC monitor signal remains asserted until the latch receives an RTC monitor reset signal from the GNSS receiver.
In the portable electronic device using the digital Real Time Clock (RTC) monitor Integrated Circuit (IC) as described in claim 1, the IC includes a latch. This latch receives the RTC reset signal and, when triggered, asserts an RTC monitor signal. This RTC monitor signal remains active, indicating a problem with the RTC, until the latch receives an RTC monitor reset signal from the GNSS receiver. This allows the GNSS receiver to acknowledge and handle the RTC fault.
4. The portable electronic device of claim 1 , wherein the digital IC further comprises: a Power-On/Reset (POR) input configured to receive a POR signal from the portable electronic device, the POR signal being asserted when the portable electronic device is reset or powered on.
In the portable electronic device using the digital Real Time Clock (RTC) monitor Integrated Circuit (IC) as described in claim 1, the IC includes a Power-On/Reset (POR) input. This input receives a POR signal from the portable electronic device, which is asserted when the device is reset or powered on. This ensures the RTC monitoring logic is properly initialized and synchronized with the device's power state.
5. An oscillator timing monitor, comprising: a resistance/capacitance (RC) oscillator configured to output a digital pulse signal; a digital Integrated Circuit (IC) configured to monitor a Real Time Clock (RTC) oscillator, the digital IC comprising: an RTC input configured to receive a timing signal output by the RTC oscillator; an RC oscillator input configured to receive the digital pulse signal from the RC oscillator; an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles or has become otherwise dysfunctional.
An oscillator timing monitor uses a digital Integrated Circuit (IC) to monitor a Real Time Clock (RTC) oscillator. An RC oscillator outputs digital pulses to the IC. The IC receives both the RTC oscillator's timing signal and the RC oscillator's pulse signal. If the IC detects that the RTC oscillator has missed clock cycles or is malfunctioning based on the comparison of the RC oscillator to the RTC oscillator, it outputs an RTC reset signal, indicating an issue with the RTC oscillator's timing.
6. The oscillator timing monitor of claim 5 , wherein the RTC oscillator is a lower power oscillator configured to maintain timing while a higher power oscillator is turned off.
The oscillator timing monitor from claim 5 uses the RTC oscillator as a low-power timing source. This RTC oscillator maintains timing when a higher-power main oscillator is turned off to save energy. The digital IC monitors this low-power RTC oscillator for errors, ensuring accurate timekeeping even during periods of reduced power consumption.
7. The oscillator timing monitor of claim 5 , wherein a frequency of the RC oscillator input is divided before processing and comparing with the RTC input by the digital IC.
In the oscillator timing monitor from claim 5, the frequency of the RC oscillator's digital pulse signal is divided before being compared to the RTC oscillator's signal by the digital IC. This allows the IC to compare the signals over a longer timescale. This division improves the accuracy of the RTC monitoring process.
8. The oscillator timing monitor of claim 5 , wherein the digital IC further comprises: a latch configured to receive the RTC reset signal and to assert and maintain a RTC monitor signal when the RTC reset signal is asserted.
In the oscillator timing monitor from claim 5, the digital IC contains a latch. The latch receives the RTC reset signal. When the RTC reset signal is asserted (meaning the RTC is faulty), the latch asserts and maintains an RTC monitor signal. This signal indicates that the RTC is experiencing timing problems and needs attention.
9. The oscillator timing monitor of claim 8 , wherein the latch is further configured to receive a monitor reset signal and de-assert the RTC monitor signal when the monitor reset signal is asserted.
In the oscillator timing monitor using the latch as described in claim 8, the latch can also receive a monitor reset signal. When this reset signal is asserted, the latch de-asserts the RTC monitor signal, clearing the indication of an RTC fault. This allows the system to acknowledge and clear the fault condition.
10. The oscillator timing monitor of claim 5 , wherein the digital IC comprises an up/down counter, and wherein the RTC input is the UP input and the RC input is the DN input to the up/down counter.
In the oscillator timing monitor from claim 5, the digital IC utilizes an up/down counter. The RTC oscillator's signal serves as the UP input to the counter, while the RC oscillator's signal acts as the DOWN input. This allows the counter to track the relative timing difference between the two oscillators.
11. The oscillator timing monitor of claim 10 , wherein the digital IC further comprises: a threshold monitor receiving the output of the up/down counter and determining whether the output of the up/down counter exceeds a threshold to generate the RTC reset output signal.
In the oscillator timing monitor using the up/down counter as described in claim 10, the digital IC also includes a threshold monitor. This monitor receives the output from the up/down counter and determines if it exceeds a certain threshold. If the counter's value exceeds the threshold (meaning the RTC is lagging behind the RC oscillator), the threshold monitor generates the RTC reset output signal, indicating a fault.
12. The oscillator timing monitor of claim 5 , wherein the digital IC further comprises: a Power-On/Reset (POR) input configured to receive a POR input.
In the oscillator timing monitor from claim 5, the digital IC includes a Power-On/Reset (POR) input. This input receives a POR signal, enabling the IC to properly initialize and synchronize its operation with the power-on or reset state of the system it's monitoring.
13. An electronic device, comprising: a first circuit comprising: a clock input for receiving a first clock signal; a transmitter for generating each of a power-on, reset, and wake-up interrupt signal, wherein each of a power-on, reset, and wake-up interrupt signal are distinguishable by at least a number of cycles of the first clock signal each of the power-on, reset, and wake-up interrupt signal is asserted; and a single pin output for transmitting the each of a power-on, reset, and wake-up interrupt signal to a second circuit; the second circuit comprising: a single pin input for receiving each power-on, reset, and wake-up interrupt signal transmitted by the first circuit; a clock input for receiving a second clock signal, the second clock signal having the same nominal frequency as the first clock signal; and a detector electrically connected to the single pin input and the clock input, the detector configured to detect each of the power-on, reset, and wake-up interrupt signals by at least a number of cycles of the second clock signal the signal is asserted; and a single line electrically connecting the single pin output of the first circuit to the single pin input of the second circuit, the single line operable to carry each of a power-on, reset, and wake-up interrupt signal from the first circuit to the second circuit.
An electronic device has two circuits that communicate using a single wire for power-on, reset, and wake-up interrupt signals. The first circuit has a clock input, a transmitter, and a single-pin output. The transmitter encodes different signals (power-on, reset, wake-up) by varying the duration (number of clock cycles asserted) of a pulse sent on the single-pin output. The second circuit has a single-pin input, a clock input synchronized with the first circuit's clock, and a detector. The detector measures the duration of the pulse received on the single-pin input, using the second clock, and identifies the signal type (power-on, reset, or wake-up) based on that duration.
14. The electronic device of claim 13 , wherein the first and second clock signals are generated by the same clock.
The electronic device from claim 13 uses the same clock to generate the first and second clock signals for the transmitting and receiving circuits, respectively. This ensures accurate synchronization for reliable signal detection based on pulse duration.
15. The electronic device of claim 13 , wherein the first clock signal is generated by a first clock and the second clock signal is generated by a second clock, wherein a maximum possible clock frequency difference caused by frequency errors of both the first and second clocks are such that clock signal pulse widths are uniquely distinguishable at both ends.
The electronic device from claim 13 uses two different clocks, a first clock in the transmitting circuit and a second clock in the receiving circuit. The maximum possible difference in frequency between these two clocks is small enough that the pulse widths for each signal type (power-on, reset, wake-up) remain uniquely distinguishable at both the transmitting and receiving ends, ensuring reliable signal detection despite clock variations.
16. The electronic device of claim 13 , wherein there are a plurality of second circuits receiving each power-on, reset, and wake-up interrupt signal transmitted by the first circuit, and wherein the single line comprises a bus.
The electronic device from claim 13 has one transmitting circuit connected to multiple receiving circuits. The single wire connecting them is implemented as a bus, allowing the first circuit to send power-on, reset, and wake-up interrupt signals to all second circuits simultaneously.
17. The electronic device of claim 13 , wherein: the single pin output of the first circuit comprises a single pin input/output for both transmitting and receiving each of a power-on, reset, and wake-up interrupt signal to and from the second circuit; the single pin input of the second circuit comprises a single pin input/output for both transmitting and receiving each of a power-on, reset, and wake-up interrupt signal to and from the first circuit; and the single line is operable to carry signals bidirectionally.
In the electronic device from claim 13, the single pin is a single pin input/output on both the first and second circuits, and the single line connecting them is bidirectional. This allows communication in both directions. The same wire is used both for transmitting power-on, reset, and wake-up signals from the first circuit to the second circuit, and for sending other signals from the second circuit back to the first.
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July 10, 2014
May 16, 2017
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