A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.
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1. A method for fabricating semiconductor device, comprising: providing a substrate having a first region and a second region; forming a shallow trench isolation (STI) in the substrate to separate the first region and the second region; forming a patterned hard mask on the first region and part of the STI, wherein the patterned hard mask comprises an opening to expose part of the STI; and driving-in a gas through the exposed STI to alter an edge of the substrate on the first region.
A method for making semiconductor devices involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A hard mask is then patterned on one region and part of the STI, with an opening that exposes part of the STI. Gas is driven through this exposed STI to modify the edge of the substrate in the first region. This process is used to fabricate semiconductor devices.
2. The method of claim 1 , further comprising: providing the gas to form a first gate dielectric layer on the second region of the substrate while driving-in the gas to alter the edge of the substrate on the first region.
This semiconductor fabrication method involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A hard mask is patterned on one region and part of the STI, exposing part of the STI. Gas is driven through the exposed STI to modify the substrate's edge in the first region. While altering the edge, the gas also forms a first gate dielectric layer on the second region of the substrate. This allows for simultaneous edge modification and dielectric layer formation.
3. The method of claim 2 , further comprising: removing the patterned hard mask after forming the first gate dielectric layer; and forming a well in the substrate of the first region.
This semiconductor fabrication method involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A hard mask is patterned on one region and part of the STI, exposing part of the STI. Gas is driven through the exposed STI to modify the substrate's edge in the first region. While altering the edge, the gas also forms a first gate dielectric layer on the second region of the substrate. Following this, the hard mask is removed, and a well is formed in the substrate of the first region. This sequence allows for controlled doping after dielectric formation and edge modification.
4. The method of claim 3 , further comprising: forming a pad layer and the patterned hard mask on the first region of the substrate and part of the STI; forming the first gate dielectric layer; removing the patterned hard mask; forming the well; and removing the pad layer.
This semiconductor fabrication method involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A pad layer and a hard mask are formed on one region and part of the STI. Gas is driven through the exposed STI to modify the substrate's edge in the first region and form a first gate dielectric layer on the second region. The hard mask is then removed, followed by forming a well in the substrate of the first region. Finally, the pad layer is removed. This complete sequence enables precise doping and dielectric formation with intermediate masking steps.
5. The method of claim 4 , further comprising forming a second gate dielectric layer on the first region of the substrate after removing the pad layer.
This semiconductor fabrication method involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A pad layer and a hard mask are formed on one region and part of the STI. Gas is driven through the exposed STI to modify the substrate's edge in the first region and form a first gate dielectric layer on the second region. The hard mask is then removed, followed by forming a well in the substrate of the first region. The pad layer is removed, and a second gate dielectric layer is formed on the first region of the substrate.
6. The method of claim 5 , wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.
This semiconductor fabrication method involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A pad layer and a hard mask are formed on one region and part of the STI. Gas is driven through the exposed STI to modify the substrate's edge in the first region and form a first gate dielectric layer on the second region. The hard mask is then removed, followed by forming a well in the substrate of the first region. The pad layer is removed, and a second gate dielectric layer is formed on the first region of the substrate. Importantly, the first gate dielectric layer is thicker than the second gate dielectric layer.
7. The method of claim 5 , further comprising: forming a gate structure on the second gate dielectric layer; and forming a diffusion region adjacent to two sides of the second gate dielectric layer.
This semiconductor fabrication method involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A pad layer and a hard mask are formed on one region and part of the STI. Gas is driven through the exposed STI to modify the substrate's edge in the first region and form a first gate dielectric layer on the second region. The hard mask is then removed, followed by forming a well in the substrate of the first region. The pad layer is removed, and a second gate dielectric layer is formed on the first region of the substrate. After this, a gate structure is formed on the second gate dielectric layer, and diffusion regions are formed adjacent to two sides of the second gate dielectric layer.
8. The method of claim 5 , wherein a distance between an edge of the opening to an edge of the diffusion region is between 0.005 μm to 0.5 μm.
This semiconductor fabrication method involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A pad layer and a hard mask are formed on one region and part of the STI. Gas is driven through the exposed STI to modify the substrate's edge in the first region and form a first gate dielectric layer on the second region. The hard mask is then removed, followed by forming a well in the substrate of the first region. The pad layer is removed, and a second gate dielectric layer is formed on the first region of the substrate. The distance between the edge of the hard mask opening (used to expose the STI) and the edge of the diffusion region is between 0.005 μm and 0.5 μm.
9. The method of claim 1 , wherein the gas comprises oxygen.
A method for making semiconductor devices involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A hard mask is then patterned on one region and part of the STI, with an opening that exposes part of the STI. Oxygen gas is driven through this exposed STI to modify the edge of the substrate in the first region. This uses oxygen as the modifying gas.
10. The method of claim 1 , further comprising altering the edge of the substrate contacting the STI so that the edge comprises a curve.
A method for making semiconductor devices involves creating a shallow trench isolation (STI) in a substrate to separate two regions. A hard mask is then patterned on one region and part of the STI, with an opening that exposes part of the STI. Gas is driven through this exposed STI to modify the edge of the substrate in the first region so that the edge contacting the STI forms a curve.
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June 2, 2016
May 16, 2017
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