A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating semiconductor device, comprising: providing a substrate having a first region and a second region; forming a shallow trench isolation (STI) in the substrate to separate the first region and the second region; forming a patterned hard mask on the first region and part of the STI, wherein the patterned hard mask comprises an opening to expose part of the STI; and driving-in a gas through the exposed STI to alter an edge of the substrate on the first region.
2. The method of claim 1 , further comprising: providing the gas to form a first gate dielectric layer on the second region of the substrate while driving-in the gas to alter the edge of the substrate on the first region.
3. The method of claim 2 , further comprising: removing the patterned hard mask after forming the first gate dielectric layer; and forming a well in the substrate of the first region.
4. The method of claim 3 , further comprising: forming a pad layer and the patterned hard mask on the first region of the substrate and part of the STI; forming the first gate dielectric layer; removing the patterned hard mask; forming the well; and removing the pad layer.
5. The method of claim 4 , further comprising forming a second gate dielectric layer on the first region of the substrate after removing the pad layer.
6. The method of claim 5 , wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.
7. The method of claim 5 , further comprising: forming a gate structure on the second gate dielectric layer; and forming a diffusion region adjacent to two sides of the second gate dielectric layer.
8. The method of claim 5 , wherein a distance between an edge of the opening to an edge of the diffusion region is between 0.005 μm to 0.5 μm.
9. The method of claim 1 , wherein the gas comprises oxygen.
10. The method of claim 1 , further comprising altering the edge of the substrate contacting the STI so that the edge comprises a curve.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 2, 2016
May 16, 2017
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