A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor structure, comprising: a substrate; a source region and a drain region formed in the substrate; a gate formed on the substrate and between the source region and the drain region; and a dummy contact formed on the substrate, the dummy contact comprising a plurality of dummy plugs, wherein the dummy plugs have depths decreasing towards the drain region.
2. The semiconductor structure according to claim 1 , further comprising: a gate contact electrically connected to the gate, wherein the dummy contact is electrically connected to the gate contact.
3. The semiconductor structure according to claim 1 , further comprising: an isolation structure formed in the substrate, wherein the dummy contact is formed apart from the isolation structure.
4. The semiconductor structure according to claim 1 , wherein the dummy plug with the smallest depth is separated from an edge of the gate by a first distance, the edge of the gate is separated from an edge of the drain region by a second distance, and a ratio of the first distance to the second distance is equal to or small than ⅔.
5. The semiconductor structure according to claim 1 , wherein the number of the dummy plugs is at least three, any two of the adjacent dummy plugs are separated by a spacing, and the spacings between the dummy plugs are the same.
6. The semiconductor structure according to claim 1 , wherein the depths of the dummy plugs are decreasing by a depth interval of 0.01-0.2μm.
7. The semiconductor structure according to claim 1 , wherein the depths of the dummy plugs are decreasing by a depth decreasing ratio of 1-30%, and the depth decreasing ratio is defined as a difference between the two depths to the larger one of the two depths of any two adjacent ones of the dummy plugs.
8. The semiconductor structure according to claim 1 , wherein the dummy plugs have widths decreasing towards the drain region.
9. The semiconductor structure according to claim 8 , wherein the widths of the dummy plugs are decreasing by a width interval of 0.01-0.1 μm.
10. The semiconductor structure according to claim 8 , wherein the widths of the dummy plugs are decreasing by a width decreasing ratio of 5-80%, and the width decreasing ratio is defined as a difference between the two widths to the larger one of the two widths of any two adjacent ones of the dummy plugs.
11. The semiconductor structure according to claim 8 , further comprising a gate contact electrically connected to the gate, wherein a width of the gate contact is larger than the widths of the dummy plugs.
12. A manufacturing method of a semiconductor structure, comprising: providing a substrate; forming a source region and a drain region in the substrate; forming a gate on the substrate and between the source region and the drain region; and forming a dummy contact on the substrate, the dummy contact comprising a plurality of dummy plugs, wherein the dummy plugs have depths decreasing towards the drain region.
13. The manufacturing method of the semiconductor structure according to claim 12 , further comprising: forming a gate contact electrically connected to the gate, wherein the dummy contact is electrically connected to the gate contact.
14. The manufacturing method of the semiconductor structure according to claim 12 , further comprising: forming an insulating material on the substrate; and forming a plurality of dummy plug holes in the insulating material, wherein the dummy plug holes have widths decreasing towards the drain region.
15. The manufacturing method of the semiconductor structure according to claim 14 , further comprising: forming a gate contact hole in the insulating material, wherein a width of the gate contact hole is larger than the widths of the dummy plug holes.
16. The manufacturing method of the semiconductor structure according to claim 12 , further comprising: forming an isolation structure in the substrate, wherein the dummy contact is formed apart from the isolation structure.
17. The manufacturing method of the semiconductor structure according to claim 12 , wherein the dummy plug with the smallest depth is separated from an edge of the gate by a first distance, the edge of the gate is separated from an edge of the drain region by a second distance, and a ratio of the first distance to the second distance is equal to or small than ⅔.
18. The manufacturing method of the semiconductor structure according to claim 12 , wherein the depths of the dummy plugs are decreasing by a depth decreasing ratio of 1-30%, and the depth decreasing ratio is defined as a difference between the two depths to the larger one of the two depths of any two adjacent ones of the dummy plugs.
19. The manufacturing method of the semiconductor structure according to claim 12 , wherein the dummy plugs have widths decreasing towards the drain region.
20. The manufacturing method of the semiconductor structure according to claim 19 , wherein the widths of the dummy plugs are decreasing by a width decreasing ratio of 5-80%, and the width decreasing ratio is defined as a difference between the two widths to the larger one of the two widths of any two adjacent ones of the dummy plugs.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 15, 2015
May 16, 2017
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