The present invention relates to a technology for providing a selection unit configured to perform selection of a bit memory that holds a signal of a first bit of a digital signal from among a plurality of bit memories commonly in a memory unit in each of a plurality of AD conversion units.
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1. An image pickup apparatus comprising: a plurality of pixels arranged in rows and columns, each of the pixels outputting a photoelectric conversion signal based on incident light; a plurality of AD conversion units, each of the AD conversion units being provided to correspond to a column of the plurality of pixels and configured to convert the photoelectric conversion signal into a digital signal having plural bit signals; and a selection unit, wherein each of the plurality of AD conversion units includes a memory unit that holds the digital signal, wherein the memory unit includes a first bit memory and a second bit memory, and wherein the selection unit performs selecting a bit memory that holds the signal of a first bit signal of the digital signal, from among the first bit memory and the second bit memory, commonly in the memory unit in each of the plurality of AD conversion units.
An image sensor device has a 2D array of pixels that output signals based on light. Each column of pixels has an Analog-to-Digital Converter (ADC) that converts the pixel signal into a digital signal consisting of multiple bits. Each ADC has a memory unit to store these bits, with at least two memory locations: a "first" and "second" bit memory. A selection unit dynamically chooses which of these two memories stores a specific bit (the "first bit signal") of the digital signal. This selection is performed identically for all ADCs in the device, allowing flexible bit storage.
2. The image pickup apparatus according to claim 1 , wherein the memory unit further includes a plurality of bit memories each of which is configured to hold one bit signal of the digital signal, and the memory unit in each of the plurality of AD conversion units includes a redundant bit memory that holds a signal of a predetermined bit signal of the digital signal as a part of the plurality of bit memories, and wherein the first bit memory is the redundant bit memory, and the second bit memory is a bit memory constituting another part of the plurality of bit memories.
In the image sensor of claim 1, the memory unit in each ADC contains multiple bit memories for storing the complete digital signal. A redundant bit memory duplicates a specific bit of the digital signal. The "first bit memory" from claim 1 is this redundant bit memory, while the "second bit memory" is a regular bit memory used for a different bit. The selection unit then decides whether to use the redundant memory or the normal memory for storing the initial "first bit signal"
3. The image pickup apparatus according to claim 1 , wherein the first bit signal is a bit signal having a lower order than a most significant bit signal, and wherein the selection unit performs one of a first operation of selecting the first bit memory as the bit memory that holds the first bit signal and selecting the second bit memory as a bit memory that holds a bit signal having a higher order than the first bit signal by one bit and a second operation of selecting the second bit memory as the bit memory that holds the first bit signal.
In the image sensor of claim 1, the "first bit signal" is a lower-order bit (less significant) of the digital signal. The selection unit performs one of two operations: (1) store the lower-order "first bit signal" in the "first bit memory" and the next higher-order bit in the "second bit memory", or (2) store the lower-order "first bit signal" in the "second bit memory". This allows swapping the storage location of a less significant bit.
4. The image pickup apparatus according to claim 1 , wherein the first bit signal is a bit signal having a lower order than a most significant bit signal, and wherein the selection unit performs one of a first operation of selecting the first bit memory as the bit memory that holds the first bit signal and selecting the second bit memory as a bit memory that holds a bit signal having a lower order than the first bit signal by one bit and a second operation of selecting the second bit memory as the bit memory that holds the first bit signal.
In the image sensor of claim 1, the "first bit signal" is a lower-order bit (less significant) of the digital signal. The selection unit performs one of two operations: (1) store the lower-order "first bit signal" in the "first bit memory" and the next lower-order bit in the "second bit memory", or (2) store the lower-order "first bit signal" in the "second bit memory". This allows swapping the storage location of a less significant bit.
5. The image pickup apparatus according to claim 3 , wherein the memory unit further includes a plurality of bit memories each of which is configured to hold one bit signal of the digital signal, and the memory unit in each of the plurality of AD conversion units includes a redundant bit memory that holds the signal of the predetermined bit signal of the digital signal as a part of the plurality of bit memories, wherein the memory unit in each of the plurality of AD conversion units includes the first bit memory and the second bit memory as another part of the plurality of bit memories, and wherein the second operation is an operation of holding the first bit signal in the second bit memory and holding the bit signal having the higher order than the first bit signal by one bit in the redundant bit memory.
In the image sensor of claim 3, each ADC's memory unit contains multiple bit memories, including a redundant memory. Operation (2) from claim 3, where the lower-order "first bit signal" is stored in the "second bit memory", also involves storing the next higher-order bit in the redundant memory. The "first" and "second" bit memories are part of the normal set of bit memories and independent from the redundant one.
6. The image pickup apparatus according to claim 4 , wherein the memory unit further includes a plurality of bit memories each of which is configured to hold one bit signal of the digital signal, and the memory unit in each of the plurality of AD conversion units includes a redundant bit memory that holds the predetermined bit signal of the digital signal as the part of the plurality of bit memories, wherein the memory unit in each of the plurality of AD conversion units includes the first bit memory and the second bit memory as another part of the plurality of bit memories, and wherein the second operation is an operation of holding the first bit signal in the second bit memory and holding the bit signal having the lower order than the first bit signal by one bit in the redundant bit memory.
In the image sensor of claim 4, each ADC's memory unit contains multiple bit memories, including a redundant memory. Operation (2) from claim 4, where the lower-order "first bit signal" is stored in the "second bit memory", also involves storing the next lower-order bit in the redundant memory. The "first" and "second" bit memories are part of the normal set of bit memories and independent from the redundant one.
7. The image pickup apparatus according to claim 3 , further comprising: an output unit, wherein the output unit rearranges an order of the plural bits signals output from the memory unit that holds the digital signal by the second operation to be matched with an order of the plural bit signals output from the memory unit in a case where the digital signal is held by the first operation.
The image sensor of claim 3 includes an output unit. If the selection unit used operation (2) from claim 3 (swapping the lower-order bit's storage), the output unit reorders the bits before outputting the digital signal to ensure the bit order matches the original order from operation (1).
8. The image pickup apparatus according to claim 4 , further comprising: an output unit, wherein the output unit rearranges an order of the plural bit signals output from the memory unit that holds the digital signal by the second operation to be matched with an order of the plural bit signals output from the memory unit in a case where the digital signal is held by the first operation.
The image sensor of claim 4 includes an output unit. If the selection unit used operation (2) from claim 4 (swapping the lower-order bit's storage), the output unit reorders the bits before outputting the digital signal to ensure the bit order matches the original order from operation (1).
9. The image pickup apparatus according to claim 1 , further comprising: a measurement counter configured to supply a count signal obtained by counting clock signals commonly to the plurality of memory units, wherein the count signal is supplied from the measurement counter to the plurality of memory units via the selection unit.
The image sensor of claim 1 includes a central counter that generates a count signal from clock pulses, and this count signal is sent to all the memory units in the ADCs. The selection unit acts as a pathway for delivering the count signal to the memory units.
10. The image pickup apparatus according to claim 1 , wherein each of the plurality of AD conversion units further includes a measurement counter configured to supply a count signal obtained by counting clock signals to the memory unit.
In the image sensor of claim 1, instead of a shared counter, each ADC has its own separate counter that generates a count signal from clock pulses, and this counter is directly connected to its corresponding memory unit.
11. An image pickup system comprising: an image pickup apparatus; and a signal processing unit configured to generate an image by processing a signal output from the image pickup apparatus, the image pickup apparatus including a plurality of pixels arranged in rows and columns, each of the pixels outputting a photoelectric conversion signal based on incident light, a plurality of AD conversion units, each of the AD conversion units being provided to correspond to a column of the plurality of pixels and configured to convert the photoelectric conversion signal into a digital signal having plural bit signals, and a selection unit, wherein each of the plurality of AD conversion units includes a memory unit that holds the digital signal, wherein the memory unit includes a first bit memory and a second bit memory, and wherein the selection unit performs selecting a bit memory that holds the signal of a first bit signal of the digital signal, from among the first bit memory and the second bit memory, commonly in the memory unit in each of the plurality of AD conversion units.
An imaging system incorporates the image sensor described in claim 1, which has a 2D array of pixels, ADCs per column with memory units storing multiple bits of the digitized pixel signal, and a selection unit to choose between two memory locations for a specific bit ("first bit signal"). The system also includes a signal processing unit that receives the output from the image sensor and constructs an image.
12. A driving method for an image pickup apparatus that includes a plurality of pixels arranged in rows and columns, each of the pixels outputting a photoelectric conversion signal based on incident light, and a plurality of AD conversion units, each of the AD conversion units being provided to correspond to a column of the plurality of pixels and configured to convert the photoelectric conversion signal into a digital signal having plural bit signals, in which each of the plurality of AD conversion units includes a memory unit that holds the digital signal, and the memory unit includes a first bit memory and a second bit memory, the driving method comprising: performing selection of a bit memory that holds a first bit signal of the digital signal, from among the first bit memory and the second bit memory, commonly in the memory unit in each of the plurality of AD conversion units.
A method for driving an image sensor with pixels, ADCs, and memory units (as described in claim 1) involves selecting which of two available bit memories (first and second) will store a specific bit ("first bit signal") of the digital signal. This selection is performed consistently across all ADCs.
13. An image pickup apparatus comprising: a plurality of pixels arranged in rows and columns, each of the pixels outputting a photoelectric conversion signal based on incident light; a plurality of AD conversion units, each AD conversion unit of which is provided to correspond to a column of the plurality of pixels, and configured to convert the photoelectric conversion signal into a digital signal having plural bit signals; a first data line; a second data line; and a selection unit, wherein the each AD conversion unit includes a memory unit that holds the digital signal, wherein the memory unit includes a first bit memory and a second bit memory, wherein the first bit memory of the AD conversion unit is connected to the first data line, wherein the second bit memory of the AD conversion unit is connected to the second data line, and wherein the selection unit is configured to select one of the first data line and the second data line as a data line for outputting a first bit signal of the digital signal to the memory unit of the each AD conversion unit.
An image sensor has a 2D array of pixels and ADCs, similar to claim 1. It includes two data lines, "first" and "second". Each ADC has a memory unit with at least two bit memories: "first" and "second". The "first bit memory" connects to the "first data line," and the "second bit memory" connects to the "second data line." A selection unit chooses either the "first" or "second" data line to output a specific bit ("first bit signal") to the memory unit of each ADC.
14. The image pickup apparatus according to claim 13 , wherein the memory unit further includes a plurality of bit memories, each of which is configured to hold one bit signal of the digital signal, and the memory unit in each of the plurality of AD conversion units includes a redundant bit memory that holds a predetermined bit signal of the digital signal as a part of the plurality of bit memories, and wherein the first bit memory is the redundant bit memory, and the second bit memory is a bit memory constituting another part of the plurality of bit memories.
In the image sensor of claim 13, each ADC memory contains multiple bit memories including a redundant memory. The "first bit memory" in each ADC (connected to the "first data line") is the redundant bit memory, and the "second bit memory" (connected to the "second data line") is a regular memory storing a different bit.
15. The image pickup apparatus according to claim 13 , wherein the first bit signal is a bit signal having a lower order than a most significant bit signal, and wherein the selection unit performs one of: a first operation of selecting the first data line as a data line for outputting the first bit signal of the digital signal to the memory unit of the each AD conversion unit, and selecting the second data line as a data line for outputting a bit signal of the digital signal having a higher order than the first bit signal to the memory unit of the each AD conversion unit, and a second operation of selecting the first data line as a data line for outputting the first bit signal of the digital signal to the memory unit of the each AD conversion unit.
In the image sensor of claim 13, the "first bit signal" is a lower-order bit. The selection unit performs one of two operations: (1) use the "first data line" to output the lower-order "first bit signal" and the "second data line" to output the next higher-order bit, or (2) use the "first data line" to output the lower-order "first bit signal".
16. The image pickup apparatus according to claim 13 , wherein the first bit signal is a bit signal having a lower order than a most significant bit signal, and wherein the selection unit performs one of: a first operation of selecting the first data line as a data line for outputting the first bit signal of the digital signal to the memory unit of the each AD conversion unit, and selecting the second data line as a data line for outputting a bit signal of the digital signal having a lower order than the first bit signal to the memory unit of the each AD conversion unit, and a second operation of selecting the first data line as a data line for outputting the first bit signal of the digital signal to the memory unit of the each AD conversion unit.
In the image sensor of claim 13, the "first bit signal" is a lower-order bit. The selection unit performs one of two operations: (1) use the "first data line" to output the lower-order "first bit signal" and the "second data line" to output the next lower-order bit, or (2) use the "first data line" to output the lower-order "first bit signal".
17. The image pickup apparatus according to claim 16 , wherein the memory unit further includes: a plurality of bit memories, each of which is configured to hold one bit signal of the digital signal, and a redundant bit memory that holds the predetermined bit signal of the digital signal as a part of the plurality of bit memories, wherein the memory unit in the each AD conversion unit includes the first bit memory and the second bit memory as another part of the plurality of bit memories, and wherein the second operation is an operation of holding the first bit signal in the second bit memory, and holding a bit signal of the digital signal having a higher order than the first bit signal, in the redundant bit memory.
In the image sensor of claim 16, each ADC has multiple bit memories including a redundant one. Operation (2) from claim 16, which uses the "first data line" for the lower-order bit, also stores the next *higher*-order bit in the redundant memory. The "first" and "second" bit memories are regular bit memories.
18. The image pickup apparatus according to claim 16 , wherein the memory unit further includes: a plurality of bit memories each of which is configured to hold one bit of the digital signal, and a redundant bit memory that holds the signal of the predetermined bit of the digital signal as the part of the plurality of bit memories, wherein the memory unit in the each AD conversion unit includes the first bit memory and the second bit memory as another part of the plurality of bit memories, and wherein the second operation is an operation of holding the signal of the first bit in the second bit memory, and holding a bit signal of the digital signal having a lower order than the first bit signal, in the redundant bit memory.
In the image sensor of claim 16, each ADC has multiple bit memories including a redundant one. Operation (2) from claim 16, which uses the "first data line" for the lower-order bit, also stores the next *lower*-order bit in the redundant memory. The "first" and "second" bit memories are regular bit memories.
19. The image pickup apparatus according to claim 13 , further comprising a third data line and a fourth data line, wherein the memory unit further includes: a plurality of bit memories, each of which is configured to hold one bit signal of the digital signal, a first redundant bit memory as the second bit memory, a second redundant bit memory connected to the fourth data line, and a third bit memory connected to the third data line, wherein the selection unit performs one of: a first operation of selecting the first data line as a data line for outputting the first bit signal of the digital signal to the memory unit of the each AD conversion unit, and selecting the third data line as a data line for outputting a second bit signal of the digital signal different from the first bit signal to the memory unit of the each AD conversion unit, and a second operation of selecting the second data line as a data line for outputting the first bit signal of the digital signal to the memory unit of the each AD conversion unit, and selecting the fourth data line as a data line for outputting the second bit signal of the digital signal to the memory unit of the each AD conversion unit.
In the image sensor of claim 13, there are *four* data lines: "first", "second", "third", and "fourth". Each ADC has multiple bit memories including two redundant memories ("first" and "second") and a third bit memory. The "first redundant bit memory" is connected to the "second data line". The "second redundant bit memory" is connected to the "fourth data line" and the "third bit memory" connects to the "third data line". The selection unit either: (1) uses the "first data line" for the "first bit signal" and the "third data line" for another bit signal, or (2) uses the "second data line" for the "first bit signal" and the "fourth data line" for the other bit signal.
20. The image pickup apparatus according to claim 16 , further comprising: an output unit, wherein the output unit rearranges an order of the plural bit signals output from the memory unit that holds the digital signal by the second operation to be matched with an order of the plural bit signals output from the memory unit in a case where the digital signal is held by the first operation.
The image sensor of claim 16 includes an output unit. If operation (2) from claim 16 was performed (swapping a bit's data line), the output unit reorders the output bits to match the order from operation (1).
21. The image pickup apparatus according to claim 16 , further comprising: an output unit, wherein the output unit rearranges an order of the plural bit signals output from the memory unit that holds the digital signal by the second operation to be matched with an order of the plural bit signals output from the memory unit in a case where the digital signal is held by the first operation.
The image sensor of claim 16 includes an output unit. If operation (2) from claim 16 was performed (swapping a bit's data line), the output unit reorders the output bits to match the order from operation (1).
22. The image pickup apparatus according to claim 17 , further comprising: an output unit, wherein the output unit rearranges an order of the plural bit signals output from the memory unit that holds the digital signal by the second operation to be matched with an order of the plural bit signals output from the memory unit in a case where the digital signal is held by the first operation.
The image sensor of claim 17 includes an output unit. If operation (2) from claim 17 was performed (storing a bit in the redundant memory), the output unit reorders the output bits to match the order from operation (1).
23. The image pickup apparatus according to claim 18 , further comprising: an output unit, wherein the output unit rearranges an order of the plural bit signals output from the memory unit that holds the digital signal by the second operation to be matched with an order of the plural bit signals output from the memory unit in a case where the digital signal is held by the first operation.
The image sensor of claim 18 includes an output unit. If operation (2) from claim 18 was performed (storing a bit in the redundant memory), the output unit reorders the output bits to match the order from operation (1).
24. The image pickup apparatus according to claim 19 , further comprising: an output unit, wherein the output unit rearranges an order of the plural bit signals output from the memory unit that holds the digital signal by the second operation to be matched with an order of the plural bit signals output from the memory unit in a case where the digital signal is held by the first operation.
The image sensor of claim 19 includes an output unit. If operation (2) from claim 19 was performed (swapping a bit's data line and using redundant memories), the output unit reorders the output bits to match the order from operation (1).
25. The image pickup apparatus according to claim 13 , further comprising: a measurement counter configured to supply a count signal obtained by counting clock signals commonly to the plurality of memory units, wherein the count signal is supplied from the measurement counter to the plurality of memory units via the selection unit.
The image sensor of claim 13 includes a central counter that generates a count signal (from clock pulses) sent to all memory units. The selection unit serves as the pathway for delivering this common count signal.
26. The image pickup apparatus according to claim 13 , wherein each of the plurality of AD conversion units further includes a measurement counter configured to supply a count signal obtained by counting clock signals to the memory unit.
In the image sensor of claim 13, each ADC has its own counter that generates a count signal from clock pulses, and this counter is connected directly to its corresponding memory unit.
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November 23, 2015
May 16, 2017
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