In some aspects, the disclosure is directed to methods and systems for sense reference generation. A first array and a second array of MTJ based cells are configured as a magnetoresistive random access memory block. The first array is matched to the second array, the first array and the second array each including rows of MTJ based cells for storing data bits. Responsive to a first row of MTJ based cells in the first array being selected for at least a first stored data bit to be read, a reference row of MTJ based cells in the second array is connected to at least a first comparator of a plurality of comparators via reference lines, to provide sense reference for determining a value of the first stored data bit. The reference lines are shorted together prior to connecting to a first input of the first comparator.
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1. A system for sense reference generation, the system comprising: a first array and a second array of magnetic tunnel junction (MTJ) based cells configured as a magnetoresistive random access memory block, the first array matched against process, voltage and temperature (PVT) variation to the second array, the first array and the second array each comprising rows of MTJ based cells for storing data bits, wherein responsive to a first row of MTJ based cells in the first array being selected for at least a first stored data bit to be read, the second array is configured to connect a reference row of MTJ based cells in the second array to at least a first comparator of a plurality of comparators via reference lines, to provide sense reference for determining a value of the first stored data bit, wherein each of the reference lines is connected via a respective multiplexer to a respective comparator, the reference lines being shorted together, via contact with an electrical connector passing through the respective multiplexers prior to connecting to a first input of the first comparator.
A memory system uses two arrays of magnetic tunnel junction (MTJ) cells to store data, forming a magnetoresistive RAM (MRAM) block. The arrays are designed to be closely matched in terms of process, voltage, and temperature (PVT) characteristics. When reading a data bit from a row in the first array, a corresponding "reference row" in the second array is used to generate a sense reference voltage. This reference row connects to comparators via reference lines. Importantly, these reference lines are shorted together through multiplexers *before* connecting to the comparator. This shorting uses an electrical connector passing through the multiplexers, ensuring a uniform reference voltage for accurate data sensing.
2. The system of claim 1 , wherein the reference row in the second array is pre-assigned to a plurality of rows of MTJ based cells in the first array including the first row of MTJ based cells.
The memory system using two arrays of magnetic tunnel junction (MTJ) cells to store data, forming a magnetoresistive RAM (MRAM) block described previously, features a "reference row" in the second array that's used to generate a sense reference voltage. This reference row isn't unique to just one row in the first array. Instead, a single reference row in the second array is pre-assigned, or shared, amongst *multiple* rows of MTJ cells within the first array, including the row being actively read. This allows the same reference to be used across a bank of data lines.
3. The system of claim 1 , wherein the reference row in the second array is selected to provide the sense reference, the reference row selected for having a position in the second array that is most similar to that of the first row within the first array.
The memory system using two arrays of magnetic tunnel junction (MTJ) cells to store data, forming a magnetoresistive RAM (MRAM) block described previously, features a "reference row" in the second array that's used to generate a sense reference voltage. Instead of always using the same row, this system *selects* the reference row to provide the most accurate sense reference. The chosen reference row has a physical location within the second array that closely mirrors the location of the data row being read in the first array. This spatial matching improves accuracy by accounting for any systematic variations across the memory chip.
4. The system of claim 1 , wherein the plurality of comparators individually provides matched bias and loading conditions to the reference lines and data lines of the first row of MTJ based cells in the first array.
The memory system using two arrays of magnetic tunnel junction (MTJ) cells to store data, forming a magnetoresistive RAM (MRAM) block described previously, connects reference rows and data lines to multiple comparators. Each comparator is designed to provide matched bias and loading conditions to both the reference lines (from the reference array) and the data lines (from the main array). This matched biasing ensures that any inherent resistance or capacitance in the lines affects both the reference and data signals equally, leading to more accurate data sensing by removing common-mode noise.
5. The system of claim 1 , wherein each of the respective multiplexers comprises a 2-to-1 multiplexer.
The memory system using two arrays of magnetic tunnel junction (MTJ) cells to store data, forming a magnetoresistive RAM (MRAM) block, uses multiplexers to connect reference lines to comparators. Specifically, each of these multiplexers is a "2-to-1" multiplexer. This means each multiplexer can select one of two input signals to pass through to its output (connected to a comparator). This claim describes the specific type of multiplexer used.
6. The system of claim 1 , wherein the first stored data bit is stored in a first MTJ based cell that connects to a second input of the first comparator via a first data line.
The memory system uses two arrays of magnetic tunnel junction (MTJ) cells to store data. When reading, a first MTJ cell in the first array contains the actual data bit being read. This data bit is connected to the *second* input of a comparator using a data line. The comparator's *first* input receives a reference voltage. By comparing the voltage from the data bit against the reference voltage, the system determines whether the stored data bit is a 0 or a 1.
7. The system of claim 6 , wherein a resistance-capacitance (RC) time constant of the first data line is matched with that of the reference lines.
In the memory system described above, a first MTJ cell stores the data bit, which connects to the comparator via a data line. To improve accuracy, the resistance-capacitance (RC) time constant of this data line is carefully matched to the RC time constant of the reference lines. Matching these RC constants ensures that the data signal and the reference signal experience similar delays and signal degradation, improving the reliability of the comparison and the overall data sensing.
8. The system of claim 1 , wherein the sense reference is provided via averaging of voltages induced across resistances of the MTJ based cells in the reference row.
The memory system generates a sense reference voltage for reading data bits by averaging the voltages across the MTJ cells in the reference row. Since MTJ cells have variable resistances based on their stored state, averaging the voltages smooths out individual cell variations, providing a more stable and reliable reference voltage for comparing against the data signal and correctly determining the bit value.
9. The system of claim 8 , wherein the reference row includes at least one error correction coding (ECC) cell or repair cell participating in the averaging of voltages.
In the memory system, the averaging of voltages across MTJ cells in the reference row is used to generate a sense reference voltage. The reference row includes at least one error correction coding (ECC) cell or repair cell. These ECC/repair cells participate in the voltage averaging, meaning they contribute to the overall reference voltage level. This helps to improve the robustness of the reference voltage against manufacturing variations or degradation of individual memory cells.
10. The system of claim 1 , wherein each MTJ based cell of the reference row may be separately set to either a low resistance or a high resistance state to achieve a desired average voltage for sense reference.
In the memory system, the sense reference voltage is generated from averaging the voltage drops of the MTJ cells in the reference row. To precisely control this average voltage, *each* MTJ cell in the reference row can be individually programmed or set to either a low resistance state or a high resistance state. This fine-grained control allows for precise adjustment of the reference voltage to optimize data sensing accuracy and adapt to variations in the manufacturing process or operating conditions.
11. A method for sense reference generation, the method comprising: selecting a first row of magnetic tunnel junction (MTJ) based cells in a first array of MTJ based cells for at least a first stored data bit to be read; and connecting, responsive to the selection, a reference row of MTJ based cells from a second array of MTJ based cells to at least a first comparator of a plurality of comparators via reference lines, to provide a sense reference for determining a value of the first stored data bit, wherein each of the reference lines is connected via a respective multiplexer to a respective comparator, the reference lines being shorted together, via contact with an electrical connector passing through the respective multiplexers prior to connecting to a first input of the first comparator, wherein the first array and the second array of MTJ based cells are configured as a magnetoresistive random access memory block, and the first array is matched against process, voltage and temperature (PVT) variation to the second array, the first array and the second array each comprising rows of MTJ based cells for storing data bits.
A method for generating a sense reference in memory systems involves: First, selecting a row of MTJ cells in a first array to read a data bit. Then, in response to that selection, connecting a reference row of MTJ cells from a *second* array to a comparator via reference lines. The reference lines are connected via multiplexers, and these lines are shorted together using an electrical connector passing through the multiplexers *before* they reach the comparator's input. The arrays are configured as an MRAM block and are matched for process, voltage, and temperature (PVT) variations.
12. The method of claim 11 , wherein the reference row in the second array is pre-assigned to a plurality of rows of MTJ based cells in the first array including the first row of MTJ based cells.
The method for generating a sense reference in memory systems that involves connecting a reference row of MTJ cells from a second array to a comparator, this reference row is not dedicated to a single row of data in the first array. Instead, the reference row in the second array is pre-assigned or shared across *multiple* rows of MTJ cells in the first array, including the specific row currently being read. This allows a single reference row to serve multiple data rows.
13. The method of claim 11 , further comprising selecting the reference row in the second array to provide the sense reference, the reference row selected for having a position in the second array that is most similar to that of the first row within the first array.
The method for generating a sense reference in memory systems connects a reference row of MTJ cells from a second array to a comparator. The method also *selects* the most appropriate reference row from the second array to use as the sense reference. The selection criteria is based on finding the reference row whose position within the second array is most similar to the position of the row currently being read in the first array. This optimizes the reference signal by accounting for spatial variations on the memory chip.
14. The method of claim 11 , wherein each of the respective multiplexers comprises a 2-to-1 multiplexer.
The method for generating a sense reference in memory systems involves connecting reference lines to a comparator through multiplexers. Specifically, *each* of these multiplexers is a 2-to-1 multiplexer. This configuration allows for selecting one of two input signals to pass through to the comparator input, giving flexibility in routing the reference signal.
15. The method of claim 11 , further comprising connecting a first MTJ based cell having the first stored data bit, to a second input of the first comparator via a first data line.
The method for generating a sense reference in memory systems involves selecting a row of MTJ cells to read, connecting a reference row to a comparator, and taking the signal from a *first* MTJ cell (containing the data bit) and connecting it to the *second* input of that same comparator using a data line. The comparator then compares the data signal against the reference signal to determine the value of the stored bit.
16. The method of claim 15 , wherein a resistance-capacitance (RC) time constant of the first data line is matched with that of the reference lines.
The method for generating a sense reference in memory systems connects a data bit from a first MTJ cell to a comparator via a data line. In order to ensure accurate comparison, the resistance-capacitance (RC) time constant of this data line is deliberately matched to the RC time constant of the reference lines carrying the reference voltage. This matching minimizes signal distortion and timing differences, leading to more reliable data sensing.
17. The method of claim 11 , further comprising providing the sense reference via averaging of voltages induced across resistances of the MTJ based cells in the reference row.
The method for generating a sense reference in memory systems uses an averaging technique. Specifically, the sense reference is created by averaging the voltages induced across the resistances of the individual MTJ cells that make up the reference row. This averaging process smooths out variations in the individual cell resistances, resulting in a more stable and representative reference voltage.
18. A system for providing sense reference, the system comprising: a first array and a second array of magnetic tunnel junction (MTJ) based cells each comprising rows of MTJ based cells for storing data bits, wherein responsive to a first row of MTJ based cells in the first array being selected for at least a first stored data bit to be read, a reference row of MTJ based cells in the second array is connected to a first comparator via reference lines, wherein each of the reference lines is connected via a respective multiplexer to a respective comparator, and the reference lines are shorted together via contact with an electrical connector passing through the respective multiplexers prior to connecting to a first input of the first comparator.
A memory system for generating a sense reference features two arrays of MTJ cells. When a row in the first array is selected for reading, a corresponding reference row in the second array is connected to a comparator via reference lines. The key is that each reference line is connected via a multiplexer to a comparator and that *all* the reference lines are shorted together, using an electrical connector passing through the multiplexers, *before* reaching the comparator's input.
19. The system of claim 18 , wherein the reference row in the second array is selected to provide the sense reference, the reference row selected for having a position in the second array that is most similar to that of the first row within the first array.
The memory system for generating a sense reference selects a reference row from the second array. It picks the reference row whose position within the second array is most similar to the position of the row currently being read in the first array. This optimizes the reference signal by accounting for spatial variations on the memory chip, allowing for better data readout.
20. The system of claim 18 , wherein each of the respective multiplexers comprises a 2-to-1 multiplexer.
The memory system for generating a sense reference connects each reference line to a comparator via multiplexers. *Each* of these multiplexers is a 2-to-1 multiplexer. This allows for a simplified and efficient switching mechanism when selecting the reference voltage.
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April 8, 2016
May 23, 2017
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