Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device, the method comprising: forming spaced apart first and second fins on a substrate; forming an isolation layer on the substrate between the first and second fins; forming a gate electrode on the isolation layer and crossing the first and second fins; forming spacers on lateral surfaces of the gate electrode and on lateral surfaces of the first and second fins; removing portions of the first and second fins to recess upper surfaces of the first and second fins below the spacers; forming source/drain regions adjacent the gate electrode on the recessed upper surfaces of the first and second fins; and after forming the source/drain regions, removing a portion of the gate electrode between the first and second fins to expose the isolation layer.
2. The method of claim 1 , wherein forming source/drain regions on the first and second fins adjacent the gate electrode comprises forming the source/drain regions by epitaxial growth.
3. The method of claim 1 , wherein removing a portion of the gate electrode between the first and second fins to expose the isolation layer comprises anisotropic dry etching the portion of the gate electrode.
4. The method of claim 1 , wherein forming the gate electrode comprises: forming a gate insulation layer on the first and second fins; forming a gate electrode layer on the gate insulation layer; and forming a hard mask layer on the gate electrode layer.
5. The method of claim 4 , wherein forming the gate electrode further comprises: patterning the hard mask layer to form a hard mask pattern; and patterning the gate insulation layer and the gate electrode layer using the hard mask pattern as a mask.
6. The method of claim 1 , wherein forming source/drain regions on the first and second fins adjacent the gate electrode is followed by removing the gate electrode and forming a gate structure including a first metal layer and a second metal layer.
7. The method of claim 1 , wherein removing portions of the first and second fins to recess upper surfaces of the first and second fins below the spacers comprises: forming a first interlayer insulation layer covering the second fin and exposing a portion of the first fin; removing a portion of the exposed first fin to recess the upper surface of the first fin; forming a second interlayer insulation layer covering the first fin and exposing a portion of the second fin; and removing a portion of the exposed second fin to recess the upper surface of the second fin.
8. The method of claim 1 , wherein the first fin is part of a PMOS transistor and wherein the second fin is part of an NMOS transistor.
9. The method of claim 8 , wherein the source/drain regions comprise a SiGe source/drain region on the first fin and a Si or SiC source/drain region on the second fin.
10. The method of claim 1 , wherein top surfaces and lateral surfaces of the first and second fins form acute angles.
11. The method of claim 1 , wherein removing the portion of the gate electrode between the first and second fins comprises: forming a first gate structure crossing the first fin; forming a second gate structure crossing the second fin; and forming a first trench between the first and second gate structures.
12. The method of claim 11 , wherein the first and second gate structures are electrically disconnected from each other.
13. The method of claim 1 , wherein the gate electrode comprises a conductive material.
14. A method of manufacturing a semiconductor device, the method comprising: forming spaced apart first and second fins on a substrate; forming an isolation layer on the substrate between the first and second fins; forming a gate electrode on the isolation layer and crossing the first and second fins; forming source/drain regions on the first and second fins adjacent the gate electrode; and after forming the source/drain regions, removing a portion of the gate electrode between the first and second fins to expose the isolation layer, wherein removing the portion of the gate electrode between the first and second fins comprises: forming a first gate structure crossing the first fin; forming a second gate structure crossing the second fin; and forming a first trench between the first and second gate structures.
15. The method of claim 14 , wherein the first and second gate structures are electrically disconnected from each other.
16. The method of claim 14 , wherein the gate electrode comprises a conductive material.
17. The method of claim 16 , wherein the conductive material comprises a conductive metal.
18. The method of claim 14 , wherein forming source/drain regions on the first and second fins adjacent the gate electrode comprises forming the source/drain regions by epitaxial growth.
19. The method of claim 14 , wherein removing the portion of the gate electrode between the first and second fins to expose the isolation layer comprises anisotropic dry etching of the portion of the gate electrode.
20. The method of claim 14 , wherein the first fin is part of a PMOS transistor and wherein the second fin is part of an NMOS transistor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 20, 2015
May 23, 2017
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