Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth.
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1. A method of manufacturing a semiconductor device, the method comprising: forming spaced apart first and second fins on a substrate; forming an isolation layer on the substrate between the first and second fins; forming a gate electrode on the isolation layer and crossing the first and second fins; forming spacers on lateral surfaces of the gate electrode and on lateral surfaces of the first and second fins; removing portions of the first and second fins to recess upper surfaces of the first and second fins below the spacers; forming source/drain regions adjacent the gate electrode on the recessed upper surfaces of the first and second fins; and after forming the source/drain regions, removing a portion of the gate electrode between the first and second fins to expose the isolation layer.
A method for building semiconductor devices involves these steps: First, create two separate, raised "fins" on a base material (substrate). Next, fill the space between these fins with an insulating material. Then, create a gate electrode (a control element) that sits on top of the insulating material and crosses over both fins. Form spacers on the sides of the gate electrode and the fins. Remove parts of the fins so the top surface is lower than the spacers. Grow source/drain regions on the recessed fin surfaces next to the gate electrode. Finally, remove the part of the gate electrode between the fins to expose the insulating material.
2. The method of claim 1 , wherein forming source/drain regions on the first and second fins adjacent the gate electrode comprises forming the source/drain regions by epitaxial growth.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, includes a process where the source/drain regions are grown directly on the fins using a technique called epitaxial growth.
3. The method of claim 1 , wherein removing a portion of the gate electrode between the first and second fins to expose the isolation layer comprises anisotropic dry etching the portion of the gate electrode.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, involves removing the part of the gate electrode between the fins by using a process called anisotropic dry etching, which etches in one direction.
4. The method of claim 1 , wherein forming the gate electrode comprises: forming a gate insulation layer on the first and second fins; forming a gate electrode layer on the gate insulation layer; and forming a hard mask layer on the gate electrode layer.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, includes creating the gate electrode by first forming a gate insulation layer on the fins, then a gate electrode layer on top of the insulation, and finally a hard mask layer on top of the electrode layer.
5. The method of claim 4 , wherein forming the gate electrode further comprises: patterning the hard mask layer to form a hard mask pattern; and patterning the gate insulation layer and the gate electrode layer using the hard mask pattern as a mask.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins (with a gate insulation layer on the fins, a gate electrode layer on top of the insulation, and a hard mask layer on top of the electrode layer), spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, includes creating the gate electrode further by shaping the hard mask layer to create a pattern, and then using that pattern to shape the gate insulation layer and the gate electrode layer underneath.
6. The method of claim 1 , wherein forming source/drain regions on the first and second fins adjacent the gate electrode is followed by removing the gate electrode and forming a gate structure including a first metal layer and a second metal layer.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, includes removing the original gate electrode after forming the source/drain regions and replacing it with a more complex gate "structure" made of a first metal layer and then a second metal layer on top of that.
7. The method of claim 1 , wherein removing portions of the first and second fins to recess upper surfaces of the first and second fins below the spacers comprises: forming a first interlayer insulation layer covering the second fin and exposing a portion of the first fin; removing a portion of the exposed first fin to recess the upper surface of the first fin; forming a second interlayer insulation layer covering the first fin and exposing a portion of the second fin; and removing a portion of the exposed second fin to recess the upper surface of the second fin.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, involves recessing the upper surfaces of the fins in a multi-step process: First, cover one fin with an insulating layer, exposing part of the other fin. Remove a portion of the exposed fin to lower its upper surface. Then, cover the first fin and expose part of the second fin. Finally, remove a portion of the now exposed second fin to lower its upper surface.
8. The method of claim 1 , wherein the first fin is part of a PMOS transistor and wherein the second fin is part of an NMOS transistor.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, includes designating one fin as part of a PMOS transistor (a type of transistor that uses positively charged carriers), while the other fin is part of an NMOS transistor (a transistor that uses negatively charged carriers).
9. The method of claim 8 , wherein the source/drain regions comprise a SiGe source/drain region on the first fin and a Si or SiC source/drain region on the second fin.
The method for building semiconductor devices where one fin is a PMOS transistor and the other is an NMOS transistor (fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer), further specifies that the source/drain regions are made of different materials: silicon-germanium (SiGe) for the PMOS fin and either silicon (Si) or silicon-carbide (SiC) for the NMOS fin.
10. The method of claim 1 , wherein top surfaces and lateral surfaces of the first and second fins form acute angles.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, describes fins that have sharp, angled edges where the top and sides meet.
11. The method of claim 1 , wherein removing the portion of the gate electrode between the first and second fins comprises: forming a first gate structure crossing the first fin; forming a second gate structure crossing the second fin; and forming a first trench between the first and second gate structures.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, details removing the gate electrode portion by making two separate gate structures, one crossing each fin, and then creating a gap or trench between these two structures.
12. The method of claim 11 , wherein the first and second gate structures are electrically disconnected from each other.
The method where the gate electrode is removed between the fins to expose the isolation layer by forming two separate gate structures crossing each fin with a trench in between (fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins), features gate structures that are electrically isolated or not connected to each other.
13. The method of claim 1 , wherein the gate electrode comprises a conductive material.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, spacers are formed, fins are recessed, source/drain regions are formed adjacent to the gate electrode on the recessed fins, and the gate electrode is removed between the fins to expose the isolation layer, uses a gate electrode made of a material that conducts electricity.
14. A method of manufacturing a semiconductor device, the method comprising: forming spaced apart first and second fins on a substrate; forming an isolation layer on the substrate between the first and second fins; forming a gate electrode on the isolation layer and crossing the first and second fins; forming source/drain regions on the first and second fins adjacent the gate electrode; and after forming the source/drain regions, removing a portion of the gate electrode between the first and second fins to expose the isolation layer, wherein removing the portion of the gate electrode between the first and second fins comprises: forming a first gate structure crossing the first fin; forming a second gate structure crossing the second fin; and forming a first trench between the first and second gate structures.
A method for building semiconductor devices includes these steps: First, create two separate, raised "fins" on a base material (substrate). Next, fill the space between these fins with an insulating material. Then, create a gate electrode (a control element) that sits on top of the insulating material and crosses over both fins. Grow source/drain regions on the fins next to the gate electrode. Finally, remove the part of the gate electrode between the fins by making two separate gate structures, one crossing each fin, and then creating a gap or trench between these two structures, to expose the insulating material.
15. The method of claim 14 , wherein the first and second gate structures are electrically disconnected from each other.
The method where the gate electrode is removed between the fins to expose the isolation layer by forming two separate gate structures crossing each fin with a trench in between (fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, source/drain regions are formed adjacent to the gate electrode on the fins), features gate structures that are electrically isolated or not connected to each other.
16. The method of claim 14 , wherein the gate electrode comprises a conductive material.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, source/drain regions are formed adjacent to the gate electrode on the fins, and the gate electrode is removed between the fins by forming two separate gate structures crossing each fin with a trench in between, uses a gate electrode made of a material that conducts electricity.
17. The method of claim 16 , wherein the conductive material comprises a conductive metal.
The method for building semiconductor devices where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins (the gate electrode is made of a material that conducts electricity), source/drain regions are formed adjacent to the gate electrode on the fins, and the gate electrode is removed between the fins by forming two separate gate structures crossing each fin with a trench in between, uses a conductive gate electrode made of a conductive metal.
18. The method of claim 14 , wherein forming source/drain regions on the first and second fins adjacent the gate electrode comprises forming the source/drain regions by epitaxial growth.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, source/drain regions are formed adjacent to the gate electrode on the fins, and the gate electrode is removed between the fins by forming two separate gate structures crossing each fin with a trench in between, includes a process where the source/drain regions are grown directly on the fins using a technique called epitaxial growth.
19. The method of claim 14 , wherein removing the portion of the gate electrode between the first and second fins to expose the isolation layer comprises anisotropic dry etching of the portion of the gate electrode.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, source/drain regions are formed adjacent to the gate electrode on the fins, and the gate electrode is removed between the fins by forming two separate gate structures crossing each fin with a trench in between, involves removing the part of the gate electrode between the fins by using a process called anisotropic dry etching, which etches in one direction.
20. The method of claim 14 , wherein the first fin is part of a PMOS transistor and wherein the second fin is part of an NMOS transistor.
The method for building semiconductor devices described previously, where fins are formed, an isolation layer is added, a gate electrode is added crossing the fins, source/drain regions are formed adjacent to the gate electrode on the fins, and the gate electrode is removed between the fins by forming two separate gate structures crossing each fin with a trench in between, includes designating one fin as part of a PMOS transistor (a type of transistor that uses positively charged carriers), while the other fin is part of an NMOS transistor (a transistor that uses negatively charged carriers).
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July 20, 2015
May 23, 2017
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