A circuit comprises a first path, a second path, a current generating circuit, and a sense amplifier. The first path has a first current having a first current value. The second path has a second current having a second current value. The current generating circuit is configured to generate a reference current having a reference current value based on the first current value and the second current value. The sense amplifier is configured to receive a third current having a third current value and to generate a logical value based on the reference current value and the third current value.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A sensing circuit comprising: a first path having a first current, the first current having a first current value based on a first logical value of a first reference cell; a second path separate from the first path, the second path having a second current, the second current having a second current value based on a second logical value of a second reference cell, the second logical value being different from the first logical value; a current generating circuit configured to generate a reference current having a reference current value based on the first current value and the second current value; and a sense amplifier configured: to generate a third current having a third current value; to generate a fourth current having a fourth current value based on the third current value; to sum, at a comparison node, the fourth current and a fifth current having a fifth current value, the fifth current being a mirror of the reference current; and a buffer configured to output a voltage on the comparison node as an output of the sensing circuit.
A sensing circuit reads data from a memory cell by comparing its current to a reference current. It has two paths: one with a current based on a "1" reference cell, and another with a current based on a "0" reference cell. A current generator creates the reference current based on the values of these two currents. A sense amplifier generates a current based on the memory cell's state, and then generates another current based on the memory cell's state. It then compares the generated current to a mirrored version of the reference current at a comparison node, and a buffer outputs the voltage at this node as the circuit's output.
2. The sensing circuit of claim 1 , wherein the first current value includes a current value of the first reference cell and is less than the reference current value; and the second current value includes a current value of the second reference cell and is greater than the reference current value.
The sensing circuit described in claim 1 operates such that the current value produced by the "1" reference cell is less than the reference current value, while the current value produced by the "0" reference cell is greater than the reference current value. Thus, the reference current lies between the current values of the two reference cells ("1" and "0").
3. The sensing circuit of claim 1 , further comprising a memory cell configured to generate the third current, wherein the first current value corresponds to a first value of the third current when the memory cell stores the first logical value; and the second current value corresponds to a second value of the third current when the memory cell stores the second logical value.
The sensing circuit described in claim 1 incorporates a memory cell that provides the current to be sensed. The current value from the memory cell will be equivalent to the "1" reference current when the memory cell stores a logical "1" and is equivalent to the "0" reference current when the memory cell stores a logical "0."
4. The sensing circuit of claim 1 , wherein the first current value and the second current value are each about half of the reference current value.
The sensing circuit described in claim 1 is designed such that the current value representing a "1" and the current value representing a "0" are each approximately half the value of the total reference current.
5. The sensing circuit of claim 1 , wherein the first current value and the second current value are each related to the reference current value based on a ratio.
The sensing circuit described in claim 1 is designed such that the current value representing a "1" and the current value representing a "0" are each related to the reference current value based on some ratio.
6. The sensing circuit of claim 1 , wherein the current generating circuit comprises a first current mirror configured to mirror the first current to a fourth current having a fourth current value; the first current value is related to the fourth current value by a first ratio; the current generating circuit further comprises a second current mirror configured to mirror the second current to a fifth current having a fifth current value; and the second current value is related to the fifth current value by a second ratio.
The sensing circuit described in claim 1 utilizes a current generating circuit that includes two current mirrors. The first mirror mirrors the current from the "1" reference cell, creating a mirrored current that is scaled by a certain ratio to the original "1" current. The second mirror mirrors the current from the "0" reference cell creating a mirrored current that is scaled by another ratio to the original "0" current.
7. The sensing circuit of claim 6 , wherein: the first ratio equals the second ratio; and the current generating circuit is further configured to generate the reference current from the fourth current and the fifth current.
In the sensing circuit described in claim 6, the scaling ratios for the first and second current mirrors are equal to each other. The current generating circuit then creates the reference current from these two mirrored (and scaled) currents from the "1" and "0" reference cells.
8. The sensing circuit of claim 1 , wherein the sense amplifier comprises a first current mirror configured to mirror the third current to the fourth current; the sense amplifier further comprises a second current mirror configured to mirror the reference current to a fifth current.
In the sensing circuit described in claim 1, the sense amplifier includes a first current mirror that mirrors the current from the memory cell to generate a fourth current. It also contains a second current mirror that mirrors the reference current to generate a fifth current. These mirrored currents are then compared.
9. The memory circuit of claim 1 , further comprising at least one of: a first stabilization circuit configured to stabilize the first current; a second stabilization circuit configured to stabilize the second current; or a third stabilization circuit configured to stabilize the third current.
The memory circuit described in claim 1 further includes stabilization circuits that maintain a stable current. There's a stabilization circuit for the "1" reference cell current, another for the "0" reference cell current, and a third for the memory cell current.
10. A sensing method comprising: generating a first current on a first path and a second current on a second path separate from the first path; generating a reference current based on the first current and the second current; and summing, at a comparison node, a third current having a value of the reference current and a fourth current having a value of a current of a selected memory cell; and outputting a voltage on the comparison node as a result of the sensing method; wherein: the first current has a first value corresponding to a value of the current of the device when the device is in a first state; and the second current has a second value corresponding to a value of the current of the device when the device is in a second state different from the first state.
A sensing method involves creating a current for "1" and a current for "0" on separate paths. It then generates a reference current derived from these two currents. To read a memory cell, it sums the reference current with the memory cell's current at a comparison node, and the voltage at this node represents the sensing result. The "1" current represents the device's value when in the "1" state, and the "0" current represents the device's value in the "0" state.
11. The sensing method of claim 10 , wherein the value of the reference current is an average of a value of the first current and a value of the second current.
In the sensing method described in claim 10, the reference current is calculated as the average of the "1" current and the "0" current.
12. The sensing method of claim 10 , wherein the device includes a memory cell; and the memory cell stores a first logical value corresponding to the first state or stores a second logical value corresponding to the second state.
In the sensing method described in claim 10, the "device" referred to is a memory cell, and the states refer to the logical values "1" and "0" stored in the memory cell.
13. The sensing method of claim 12 , further comprising: generating a fifth current based on the first current; and generating a sixth current based on the second current, wherein generating the reference current is based on the fifth current and the sixth current.
The sensing method described in claim 12 enhances reference current generation by first creating intermediate currents based on the "1" and "0" currents, and then generating the final reference current from those intermediate values.
14. The sensing method of claim 10 further comprising: mirroring the reference current to obtain the third current; and mirroring the current of the selected memory cell to obtain the fourth current.
The sensing method described in claim 10 uses current mirrors. It mirrors the reference current to generate the "third current" used in the comparison, and it mirrors the current from the memory cell being read to generate the "fourth current" used in the comparison.
15. The sensing method of claim 10 , further comprising: stabilizing at least one of the first current, the second current or a current of a device.
The sensing method described in claim 10 incorporates current stabilization. This can involve stabilizing the "1" current, the "0" current, or the current from the device (e.g. memory cell) being sensed.
16. A memory-sensing circuit comprising: a plurality of memory cells; a plurality of first reference cells programmed to a first logical value, each of the first reference cells being configured to generate a first current; a plurality of second reference cells programmed to a second logical value, wherein the first logical value is different from the second logical value, each of the second reference cells being configured to generate a second current; a first selection circuit configured to select a memory cell of the plurality of memory cells; a second selection circuit configured to select a first reference cell of the plurality of first reference cells; a third selection circuit configured to select a second reference cell of the plurality of second reference cells; a current generating circuit configured to generate a reference current based on the selected first reference cell and the selected second reference cell, wherein the selected first reference cell is on a current path separate from a current path of the selected second reference cell; a sense amplifier configured to sum, at a comparison node, a third current having a value of the reference current and a fourth current having a value of a current of the selected memory cell; and a buffer configured to output a voltage on the comparison node as an output of the memory-sensing circuit.
A memory-sensing circuit reads multiple memory cells by comparing their current to a reference current. It includes multiple "1" reference cells, multiple "0" reference cells, and selection circuits to pick one of each, as well as the memory cell to be read. A current generator creates the reference current based on the selected "1" and "0" reference cells. A sense amplifier sums the reference current with the memory cell's current at a comparison node, and a buffer outputs the voltage at this node as the circuit's output. The "1" and "0" reference cells are on separate current paths.
17. The memory-sensing circuit of claim 16 , further comprising a first circuit configured to generate a current having half a value of a current of the selected first reference cell; and a second circuit configured to generate a current having half a value of a current of the selected second reference cell, wherein the current generating circuit is further configured to generate the reference current based on the current having half a value of the current of the selected first reference cell and on the current having half a value of the current of the selected second reference cell.
The memory-sensing circuit described in claim 16 creates the reference current by first halving the current values of the selected "1" and "0" reference cells. The current generating circuit then generates the reference current based on these halved current values.
18. The memory-sensing circuit of claim 17 , further comprising a third circuit configured to generate the fourth current having the value of the current of the selected memory cell; and a fourth circuit configured to generate the third current having a value of the reference current.
The memory-sensing circuit described in claim 17 has additional circuitry to generate the comparison currents. One circuit generates the current to be compared by using the selected memory cell's current. The other circuit generates the reference current.
19. The memory-sensing circuit of claim 16 , further comprising at least one of: a first stabilization circuit configured to stabilize a current of the selected first reference cell; a second stabilization circuit configured to stabilize a current of the selected second reference cell; or a third stabilization circuit configured to stabilize the current of the selected memory cell.
The memory-sensing circuit described in claim 16 further includes stabilization circuits. There is a stabilization circuit to keep the selected "1" reference cell's current stable, another for the selected "0" reference cell's current, and a third to stabilize the current from the memory cell being read.
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September 11, 2013
May 30, 2017
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