In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period. Each control circuit further switches a corresponding memory cell array into a sleep mode in response to all states of the enable signal in the corresponding second FIFO buffer being in a non-enabled state.
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1. A circuit arrangement, comprising: a plurality of memory cell arrays addressed by a first portion of an input address, and memory cells within each memory cell array addressed by a second portion of the input address; a first first-in-first-out (FIFO) buffer coupled to the plurality of memory cell arrays, wherein the first FIFO buffer is configured and arranged to delay the second portion of the input address to the plurality of memory cell arrays for a sleep period; a plurality of control circuits coupled to the plurality of memory cell arrays, respectively, each control circuit including a respective second FIFO buffer and configured and arranged to: decode the first portion of the input address and generate a corresponding state of an enable signal, store the corresponding state of the enable signal in the respective second FIFO buffer concurrently with input of the second portion of the input address to the first FIFO buffer, wherein the second FIFO buffer is configured and arranged to delay output of the corresponding state of the enable signal to the respective memory cell array for the sleep period, and switch the respective memory cell array into a sleep mode in response to all states of the enable signal in the second FIFO buffer being in a non-enabled state.
A memory system reduces power consumption by using FIFOs to control sleep modes in memory cell arrays. The system has multiple memory arrays, each addressed by parts of an input address. A first FIFO delays the part of the address selecting cells *within* an array. Each array has a control circuit with its own second FIFO. This circuit decodes the part of the address selecting the *array itself* and generates an enable signal. The enable signal's state is stored in the second FIFO, also delaying it. If the second FIFO contains *only* disabled states, the control circuit puts the array into a low-power sleep mode.
2. The circuit arrangement of claim 1 , wherein each control circuit is further configured and arranged to: switch the respective memory cell array into a standby mode in response to a state of the enable signal at a selected position in the second FIFO buffer being in an enabled state, and the selected position in the second FIFO buffer allowing the memory cell array to transition from the sleep mode to the standby mode before the state of the enable signal output from the second FIFO buffer is input to the respectively coupled memory cell array.
The memory system from the previous description can also enter a standby mode. If a specific position within the control circuit's FIFO has an *enabled* state, the array transitions to standby *before* the enable signal actually reaches the array. This allows the array to "wake up" earlier, improving response time without significantly increasing power consumption, enabling a smoother transition from sleep to active.
3. The circuit arrangement of claim 1 , wherein the second FIFO buffer is a latch-based RAM.
In the memory system, the second FIFO buffers, responsible for delaying the enable signals to memory arrays, are specifically implemented as latch-based RAM. This choice allows for efficient storage and retrieval of enable signal states, contributing to the overall power management strategy of the system by enabling quick transitions between sleep and active modes based on the address decoding.
4. The circuit arrangement of claim 1 , wherein the second FIFO buffer includes a plurality of serially connected flip-flops.
In the memory system, the second FIFO buffers, used to delay enable signals, consist of multiple flip-flops chained together. This serial connection of flip-flops provides a simple and reliable way to delay the enable signals, allowing the memory arrays to be selectively powered down based on address activity and optimizing power consumption.
5. The circuit arrangement of claim 1 , further comprising: a register configurable with a FIFO depth value; and a first depth-control circuit coupled to the register and to a plurality of stages of the first FIFO buffer, the first depth-control circuit configured and arranged to control depth of the first FIFO buffer by selection of output from one of the plurality of stages of the first FIFO buffer in response to the FIFO depth value; and wherein each control circuit of the plurality of control circuits includes a respective second depth-control circuit coupled to the register and to a plurality of stages of the second FIFO buffer, each second depth-control circuit configured and arranged to control depth of the second FIFO buffer by selection of output from one of the plurality of stages of the second FIFO buffer in response to the depth value.
The memory system dynamically adjusts the sleep period by changing the FIFO depth. A register stores a "depth value". First and second "depth-control" circuits, linked to the register and the FIFOs (the address FIFO and the enable signal FIFOs), select the output from a specific stage of each FIFO, based on the depth value. By changing the depth, the system alters how long the address and enable signals are delayed, tuning the duration of the sleep period to achieve the desired balance between power savings and performance.
6. The circuit arrangement of claim 1 , wherein: the plurality of memory cell arrays are arranged in a matrix having rows and columns of the memory cell arrays; and cascade circuitry in each column is configured and arranged to propagate the second portion of the input address output from the first FIFO buffer from a first memory cell array in the column to a last memory cell array in the column.
The memory system arranges the memory cell arrays in a matrix (rows and columns). "Cascade circuitry" in each column propagates the lower address portion (the part delayed by the first FIFO) from the first array in the column to the last. This arrangement streamlines address delivery within a column, simplifying the overall memory system design.
7. The circuit arrangement of claim 6 , further comprising: a plurality of column-holding circuits coupled to the cascade circuitry of the columns, respectively, each column-holding circuit coupled to receive enable signal states output from the respective second FIFO buffers of the memory cell arrays in the respective column; wherein each column-holding circuit is configured and arranged to: pass a second address portion output from the first FIFO buffer to the cascade circuitry of the respective column in response to one of the enable signal states enabling one of the memory cell arrays of the respective column; and hold address signal lines of the respective cascade circuitry in a steady state in response to none of the enable signal states enabling any of the memory cell arrays of the respective column.
The memory system from the previous description includes "column-holding circuits" that manage address signals in each column of memory arrays. Each column-holding circuit receives enable signals from the second FIFOs of arrays in its column. If *any* enable signal is active, the circuit passes the delayed address portion to the cascade circuitry. If *no* enable signal is active (meaning no array in that column needs access), the circuit holds the address lines in a steady state, further reducing power consumption by preventing unnecessary switching.
8. The circuit arrangement of claim 1 , wherein: each control circuit includes an address decoder, and each address decoder is configured and arranged to generate the corresponding state of the enable signal in response to the first portion of the input address and a state of a global enable signal.
The memory system's control circuits include address decoders. Each decoder receives the upper portion of the address (the part that selects the array) and a "global enable" signal. Based on these inputs, the decoder generates the enable signal, which is then fed into the second FIFO. This allows external control to globally enable or disable the power-saving mechanism.
9. The circuit arrangement of claim 1 , wherein: each memory cell array includes a sleep pin; each control circuit includes: a detection circuit coupled to the second FIFO buffer and configured and arranged to generate a first sleep signal in response to all states of the enable signal in the second FIFO buffer being in the non-enabled state; a selection circuit coupled to the sleep pin and coupled to receive the first sleep signal from the detection circuit and to receive a second sleep signal, wherein the selection circuit is configured and arranged to select between the first and second sleep signals and provide a selected one of the first and second sleep signals to the sleep pin.
Each memory array has a "sleep pin" to control its power state. The control circuit includes a "detection circuit" that monitors the second FIFO. If the FIFO contains *only* disabled states, the detection circuit generates a "first sleep signal". A "selection circuit" then chooses either the first sleep signal OR a "second sleep signal" (presumably from another control source) to send to the array's sleep pin. This provides flexibility in controlling the sleep mode based on both local FIFO state and potentially other system-level factors.
10. The circuit arrangement of claim 1 , wherein each memory cell array of the plurality of memory cell arrays is a dual port memory having a first port and a second port, and the circuit arrangement further comprising: a third FIFO buffer coupled to the second ports of the plurality of memory cell arrays and configured and arranged to delay the second portion of the input address to the second port the plurality of memory cell arrays for the sleep period; wherein the first FIFO buffer is coupled to the first ports of the plurality of memory cell arrays; wherein each control circuit further includes a fourth FIFO buffer and is further configured and arranged to: decode the first portion of the input address to the first port and generate a corresponding state of a first-port enable signal, decode the first portion of the input address to the second port and generate a corresponding state of a second-port enable signal, store in the second FIFO buffer concurrent with input to the first FIFO buffer of the second portion of the input address to the first port, the corresponding state of the first-port enable signal, store in the fourth FIFO buffer concurrent with input to the second FIFO buffer of the second portion of the input address to the second port, the corresponding state of the second-port enable signal, and switch the respective memory cell array into a sleep mode in response to all states of the first-port enable signal in the second FIFO buffer and all states of the second-port enable signal in the fourth FIFO buffer being in a non-enabled state.
The memory arrays are dual-port, meaning each array has two independent access ports. A third FIFO delays the address portion for the second port, mirroring the first FIFO. Control circuits now have a *fourth* FIFO. They decode the address for *both* ports, creating separate enable signals. The second FIFO stores the first-port enable signal, while the fourth FIFO stores the second-port enable signal. The array enters sleep mode ONLY if *both* the second AND fourth FIFOs contain only disabled states. This ensures that both ports are inactive before the array powers down.
11. The circuit arrangement of claim 10 , wherein each control circuit is further configured and arranged to: switch the respectively coupled memory cell array into a standby mode in response to a state of the first-port enable signal at a position in the second FIFO buffer being in an enabled state or a state of the second-port enable signal at a position in the fourth FIFO buffer being in an enabled state, and the position in the second FIFO buffer and the position in the fourth FIFO buffer allowing the memory cell array to transition from the sleep mode to the standby mode before the state of the first-port enable signal exits the second FIFO buffer and the second-port enable signals exits the fourth FIFO buffer.
The dual-port memory system from the previous description can enter a standby mode. If either the first-port enable signal (in the second FIFO) OR the second-port enable signal (in the fourth FIFO) is active at a specific, pre-determined position in its respective FIFO, the memory array transitions to standby mode. This pre-emptive wake-up allows the array to be ready for access on either port, minimizing latency while still saving power when both ports are idle.
12. A method of controlling power modes on a plurality of memory cell arrays, comprising: inputting a sequence of addresses to a plurality of memory cell arrays, each address including a first portion that addresses the memory cell arrays and a second portion that addresses memory cells within each memory cell array; storing second portions of the sequence of addresses in a first first-in-first-out (FIFO) buffer; delaying input of the second portion of each input address to the plurality of memory cell arrays for a sleep period by the first FIFO buffer; decoding the first portion of each address at a plurality of control circuits coupled to the plurality of memory cell arrays, respectively, and generating corresponding states of enable signals based on the decoded first portion of each address; storing the corresponding states of the enable signals in a plurality of second FIFO buffers, respectively, concurrently with input of the second portion of each input address to the first FIFO buffer, wherein each second FIFO buffer is configured and arranged to delay output of the corresponding state of the enable signal to a respective one of the memory cell arrays for the sleep period; and switching a respective one of the memory cell arrays into a sleep mode in response to all states of the enable signal in the respective second FIFO buffer being in a non-enabled state.
A power-saving method for memory systems involves addresses divided into array-select and cell-select portions. The cell-select portion is delayed by a first FIFO. Control circuits decode the array-select portion to generate enable signals, which are stored in second FIFOs, also delaying them. A memory array enters a sleep mode only when its corresponding second FIFO contains solely disabled states.
13. The method of claim 12 , further comprising: switching a respective one of the memory cell arrays into a standby mode in response to a state of the enable signal at a position in the respective one of the second FIFO buffers being in an enabled state, wherein the position in the second FIFO buffer allows the memory cell array to transition from the sleep mode to the standby mode before the state of the enable signal output from the second FIFO buffer is input to the respectively one of the memory cell arrays.
The method described in the previous claim also includes a standby mode. A memory array enters standby when an enable signal in its second FIFO becomes active *before* it's needed. This allows the array to wake up early, reducing access latency without negating the power savings.
14. The method of claim 12 , wherein the storing the corresponding states of the enable signals in a plurality of second FIFO buffers includes storing the corresponding states of the enable signals in a plurality of latch-based RAMs.
The enable signal states in the previous method are stored in the second FIFOs using latch-based RAM, allowing for efficient management of enable signal delays and enabling the memory arrays to respond quickly to transitions between active and low-power states.
15. The method of claim 12 , wherein the storing the corresponding states of the enable signals in a plurality of second FIFO buffers includes storing the corresponding states of the enable signals in respective pluralities of serially connected flip-flops.
In the power-saving method, the enable signal states are stored in second FIFOs using serially connected flip-flops. This simple implementation provides a reliable delay mechanism for the enable signals, enabling the selective power-down of memory arrays based on address activity.
16. The method of claim 12 , wherein the first FIFO buffer includes a plurality of stages, and each second FIFO buffer includes the plurality of stages, and the method further comprising: selecting output from one of the plurality of stages of the first FIFO buffer as output from the first FIFO buffer in response to a depth value stored in a register; selecting output from one of the plurality of stages of each second FIFO buffer as output from the second FIFO buffer in response to the FIFO depth value.
The power-saving method dynamically adjusts the sleep period. The depth of both the first (address) and second (enable) FIFOs is controlled by a depth value stored in a register. By selecting the output from a particular stage of each FIFO, the delay, and thus the sleep period, can be tuned.
17. The method of claim 12 , wherein the plurality of memory cell arrays are arranged in a matrix having rows and columns of the memory cell arrays, and the method further comprising: propagating the each second portion of an address output from the first FIFO buffer circuit from a first memory cell array in the column to a last memory cell array in the column.
In the power-saving method, the memory cell arrays are arranged in a matrix. The cell-select address portion from the first FIFO is propagated down each column, from the first array to the last.
18. The method of claim 17 , further comprising: receiving at each column-holding circuit of a plurality of column-holding circuits coupled to the memory cell arrays in the columns, respectively, enable signal states output from the second FIFO buffers coupled to the memory cell arrays in the respective column; passing, by each column-holding circuit, a second address portion output from the first FIFO buffer to the memory cell arrays in the respective column in response to one of the enable signal states enabling one of the memory cell arrays of the respective column; and holding, by each column-holding circuit, address signal lines to the memory cell arrays in the respective column in a steady state in response to none of the enable signal states enabling any of the memory cell arrays of the respective column.
The power-saving method utilizes column-holding circuits. Each circuit receives enable signal states from arrays in its column. If any enable signal is active, the circuit passes the delayed cell-select address portion. If no enable signals are active, the circuit holds the address lines steady, preventing unnecessary switching and reducing power consumption.
19. The method of claim 12 , wherein: the decoding the first portion of each address includes determining a match state based on the first portion of each address and an identifier of each memory cell array; and the generating the corresponding states of enable signals includes generating the corresponding state of each enable signal in response to the match state and a state of a global enable signal.
The decoding process in the power-saving method involves comparing the array-select address portion with an identifier for each memory array. The enable signal is then generated based on whether there's a match AND the state of a global enable signal.
20. The method of claim 12 , wherein each memory cell array includes an associated sleep pin, and the method further comprising: generating in association with each memory cell array, a respective first sleep signal in response to all corresponding states of the enable signal in the respective second FIFO buffer being in the non-enabled state; selecting between the respective first sleep signal and a second sleep signal for input to the associated sleep pin of the memory cell array.
In the power-saving method, each memory array has a sleep pin. A "first sleep signal" is generated when all enable signals in its corresponding second FIFO are disabled. The actual sleep pin receives either this first sleep signal or a "second sleep signal," allowing for flexible sleep control.
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May 9, 2016
May 30, 2017
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