To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device comprising: a first transistor, a channel region of the first transistor comprising an oxide semiconductor; a second transistor; a capacitor, one electrode of the capacitor electrically connected to one of a source and a drain of the first transistor and a gate of the second transistor; a word line electrically connected to a gate of the first transistor; a first wiring electrically connected to one of a source and a drain of the second transistor; a bit line electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor; a capacitor line electrically connected to the other electrode of the capacitor; a driver directly connected to the first wiring, the driver including a decoder, a switch circuit, a third transistor, a fourth transistor, a second wiring, and a third wiring; and an A/D converter directly connected to the first wiring, wherein the second wiring is capable of supplying a first potential, wherein the third wiring is capable of supplying a second potential different from the first potential, wherein the decoder is electrically connected to the first wiring through the switch circuit, wherein the second wiring is directly connected to the first wiring through the third transistor, and wherein the third wiring is directly connected to the first wiring through the fourth transistor.
The semiconductor device comprises a memory cell and a driver/ADC circuit. The memory cell has a first transistor (Tr) with an oxide semiconductor channel, a second Tr, and a capacitor. One capacitor electrode connects to the first Tr's source/drain and the second Tr's gate. A word line controls the first Tr. A first wiring connects to one of the second Tr's source/drain. A bit line connects to the other source/drain of both the first and second Trs. The other capacitor electrode connects to a capacitor line. The driver/ADC circuit includes a driver directly connected to the first wiring that has a decoder, a switch circuit, a third Tr, a fourth Tr, a second wiring carrying a first potential, and a third wiring carrying a second, different potential. The decoder connects to the first wiring via the switch. The second and third wirings directly connect to the first wiring through the third and fourth Trs, respectively. An A/D converter is directly connected to the first wiring.
2. The semiconductor device according to claim 1 , wherein the A/D converter is configured to convert a potential of the first wiring into a digital value and output the digital value outside.
The semiconductor device, as described previously, includes an A/D converter that converts the electrical potential of the first wiring into a digital value and transmits this digital value to external components. This allows the device to output a digital representation of the stored data on the first wiring. The memory cell has a first transistor (Tr) with an oxide semiconductor channel, a second Tr, and a capacitor. One capacitor electrode connects to the first Tr's source/drain and the second Tr's gate. A word line controls the first Tr. A first wiring connects to one of the second Tr's source/drain. A bit line connects to the other source/drain of both the first and second Trs. The other capacitor electrode connects to a capacitor line. The driver/ADC circuit includes a driver directly connected to the first wiring that has a decoder, a switch circuit, a third Tr, a fourth Tr, a second wiring carrying a first potential, and a third wiring carrying a second, different potential. The decoder connects to the first wiring via the switch. The second and third wirings directly connect to the first wiring through the third and fourth Trs, respectively.
3. The semiconductor device according to claim 1 , wherein the second transistor is an n-channel transistor.
The semiconductor device, as previously described, utilizes an n-channel transistor as the second transistor in the memory cell. The memory cell has a first transistor (Tr) with an oxide semiconductor channel, a second Tr, and a capacitor. One capacitor electrode connects to the first Tr's source/drain and the second Tr's gate. A word line controls the first Tr. A first wiring connects to one of the second Tr's source/drain. A bit line connects to the other source/drain of both the first and second Trs. The other capacitor electrode connects to a capacitor line. The driver/ADC circuit includes a driver directly connected to the first wiring that has a decoder, a switch circuit, a third Tr, a fourth Tr, a second wiring carrying a first potential, and a third wiring carrying a second, different potential. The decoder connects to the first wiring via the switch. The second and third wirings directly connect to the first wiring through the third and fourth Trs, respectively. An A/D converter is directly connected to the first wiring.
4. The semiconductor device according to claim 1 , wherein the second transistor is a p-channel transistor.
The semiconductor device, as previously described, utilizes a p-channel transistor as the second transistor in the memory cell. The memory cell has a first transistor (Tr) with an oxide semiconductor channel, a second Tr, and a capacitor. One capacitor electrode connects to the first Tr's source/drain and the second Tr's gate. A word line controls the first Tr. A first wiring connects to one of the second Tr's source/drain. A bit line connects to the other source/drain of both the first and second Trs. The other capacitor electrode connects to a capacitor line. The driver/ADC circuit includes a driver directly connected to the first wiring that has a decoder, a switch circuit, a third Tr, a fourth Tr, a second wiring carrying a first potential, and a third wiring carrying a second, different potential. The decoder connects to the first wiring via the switch. The second and third wirings directly connect to the first wiring through the third and fourth Trs, respectively. An A/D converter is directly connected to the first wiring.
5. The semiconductor device according to claim 1 , wherein a channel region of the second transistor includes silicon.
The semiconductor device, as described previously, uses a second transistor whose channel region is made of silicon. The memory cell has a first transistor (Tr) with an oxide semiconductor channel, a second Tr, and a capacitor. One capacitor electrode connects to the first Tr's source/drain and the second Tr's gate. A word line controls the first Tr. A first wiring connects to one of the second Tr's source/drain. A bit line connects to the other source/drain of both the first and second Trs. The other capacitor electrode connects to a capacitor line. The driver/ADC circuit includes a driver directly connected to the first wiring that has a decoder, a switch circuit, a third Tr, a fourth Tr, a second wiring carrying a first potential, and a third wiring carrying a second, different potential. The decoder connects to the first wiring via the switch. The second and third wirings directly connect to the first wiring through the third and fourth Trs, respectively. An A/D converter is directly connected to the first wiring.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 18, 2014
May 30, 2017
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