Methods for dynamically programming and dynamically reading one or more resistive change elements within a resistive change element array are disclosed. These methods include first pre-charging all of the array lines within a resistive change element array simultaneously and then grounding certain array lines while allowing other array lines to float in order to direct discharge currents through only selected cells. In this way, resistive change elements within resistive change element arrays made up of 1-R cells—that is, cells without in situ selection circuitry—can be reliably and rapidly accessed and programmed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A resistive change element array comprising: a plurality of word lines; a plurality of bit lines; a plurality of reference bit lines; a plurality of resistive change elements, wherein each resistive change element has a first terminal and a second terminal and wherein said first terminal of each resistive change element is in electrical communication with a word line and said second terminal of each resistive change element is in electrical communication with a bit line; a plurality of resistive reference elements, wherein each resistive reference element has a first terminal and a second terminal and wherein said first terminal of each resistive reference element is in electrical communication with a word line and said second terminal of each resistive reference element is in electrical communication with a reference bit line; a memory operation circuit operably coupled to said plurality of word lines, said plurality of bit lines, and said plurality of reference bit lines, said memory operation circuit including circuitry capable of providing a discharge current through at least one selected resistive change element and a discharge current through at least one selected resistive reference element; wherein each of said resistive change elements is adjustable between a first non-volatile resistive state and a second non-volatile resistive state responsive to electrical stimuli applied to said plurality of word lines and said plurality of bit lines; wherein each of said resistive change elements has a fixed electrical resistance value that is less than said first non-volatile resistive stat and greater than said second non-volatile resistive state.
2. The resistive change element array of claim 1 wherein said memory operation circuit includes circuitry capable of providing said discharge current through said at least one selected resistive change element and said discharge current through said at least one selected resistive reference element simultaneously within a single operation.
3. The resistive change element array of claim 1 wherein said memory operation circuit includes circuitry capable of providing said discharge current through said at least one selected resistive change element and said discharge current through said at least one selected resistive reference element sequentially within multiple operations.
4. The resistive change element array of claim 1 wherein said memory operation circuit includes circuitry capable of comparing said discharge current provided through said at least one selected resistive change element and said discharge current through at least one selected resistive reference element to determine the resistive state of said at least one resistive change element.
5. The resistive change element array of claim 4 wherein said memory operation circuit includes circuitry capable of determining the resistive state of at least two selected resistive change elements within a single operation.
6. The resistive change element array of claim 4 wherein said memory operation circuit includes circuitry capable of determining the resistive state of every resistive change element on a selected word line within a single operation.
7. The resistive change element array of claim 1 wherein said discharge currents do not significantly alter the state of said at least one resistive change element.
8. The resistive change element array of claim 1 wherein said first non-volatile resistive state corresponds to a first logic value and said second non-volatile resistive state corresponds to a second logic value.
9. The resistive change element array of claim 1 wherein said first non-volatile resistive state is at least ten times larger than said second non-volatile resistive state.
10. The resistive change element array of claim 1 wherein said first non-volatile resistive state is on the order of 10 MΩ.
11. The resistive change element array of claim 1 wherein said second non-volatile resistive state is on the order of 100 kΩ.
12. The resistive change element array of claim 1 wherein said resistive change elements are two-terminal nanotube switching elements.
13. The resistive change element array of claim 12 wherein said two-terminal nanotube switching elements comprise a nanotube fabric.
14. The resistive change element array of claim 1 wherein said resistive change elements are metal oxide memory elements.
15. The resistive change element array of claim 1 wherein said resistive change elements are phase change memory elements.
16. The resistive change element array of claim 1 wherein each of said resistive change elements is uniquely addressable by a word line and bit line combination.
17. The resistive change element array of claim 1 wherein said resistive change element array is a memory array.
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January 12, 2016
May 30, 2017
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