A method of fabricating a metal-insulator-metal (MIM) capacitor structure on a substrate includes forming a patterned metal layer over the substrate; forming an insulator layer over the patterned metal layer; forming a second metal layer over the insulator layer; removing part of the insulating layer and part of the second metal layer thereby forming a substantially coplanar surface that is formed by the patterned metal layer, the insulator layer, and the second metal layer; removing a portion of the second metal layer and a portion of the patterned metal layer to form a fin from the insulator layer that protrudes beyond the first metal layer and the second metal layer; and forming an inter-metal dielectric layer over the fin.
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1. A method comprising: forming a first metal layer over a substrate; forming an insulator layer over the first metal layer and directly on the substrate such that the insulator layer physically contacts the substrate, wherein the first metal layer is disposed along a first sidewall of the insulator layer; forming a second metal layer along a second sidewall of the insulator layer such that a first surface of the first metal layer is substantially coplanar with a second surface of the second metal layer, wherein the second sidewall of the insulator layer opposes the first sidewall of the insulator layer; etching the first metal layer and the second metal layer to form a fin feature from the insulator layer that protrudes beyond the first metal layer and the second metal layer; and forming a first via and a second via that are each coupled to the first metal layer and the second metal layer respectively.
A method for making a metal-insulator-metal (MIM) capacitor involves depositing a first metal layer on a substrate, followed by an insulator layer that directly contacts the substrate. The first metal layer is positioned along one side of the insulator layer. Then, a second metal layer is deposited along the opposite side of the insulator layer, creating a structure where the top surfaces of both metal layers are level (coplanar). The metal layers are then etched to create a fin, where the insulator layer extends beyond the metal layers. Finally, conductive vias are formed to connect to each metal layer.
2. The method of claim 1 , wherein the forming the second metal layer includes: forming the second metal layer over the insulator layer; and removing part of the insulating layer and part of the second metal layer.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate with the first metal layer on one side, and a second metal layer on the opposite side with coplanar surfaces, etched to create an insulator fin, and vias formed to each metal layer, forms the second metal layer by initially depositing it over the entire insulator layer. Part of both the insulator and second metal layer are then removed to achieve the coplanar surface.
3. The method of claim 2 , wherein the removing includes a chemical-mechanical planarization (CMP) process.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate with the first metal layer on one side, and a second metal layer on the opposite side, deposited over the entire insulator layer before being planarized, etched to create an insulator fin, and vias formed to each metal layer, achieves the planarization step using a chemical-mechanical planarization (CMP) process.
4. The method of claim 3 , wherein the first via and the second via share a same height.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate with the first metal layer on one side, and a second metal layer on the opposite side, deposited over the entire insulator layer before being planarized using CMP, etched to create an insulator fin, and vias formed to each metal layer, includes vias connecting to each metal layer that have the same depth.
5. The method of claim 1 , wherein, from a top view, the first metal layer, the insulator layer, and the second metal layer are concentric circles.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate with the first metal layer on one side, and a second metal layer on the opposite side with coplanar surfaces, etched to create an insulator fin, and vias formed to each metal layer, features a layout where the metal and insulator layers are arranged as concentric circles when viewed from above.
6. The method of claim 1 , wherein, from a top view, each of the first metal layer, the insulator layer, and the second metal layer form a polygon shape.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate with the first metal layer on one side, and a second metal layer on the opposite side with coplanar surfaces, etched to create an insulator fin, and vias formed to each metal layer, features metal and insulator layers shaped as polygons when viewed from above.
7. The method of claim 6 , wherein the polygon shape includes at least one rounded corner.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate with the first metal layer on one side, and a second metal layer on the opposite side with coplanar surfaces, etched to create an insulator fin, and vias formed to each metal layer, features metal and insulator layers shaped as polygons with rounded corners when viewed from above.
8. A method of fabricating a metal-insulator-metal (MIM) capacitor structure on a substrate, comprising: forming a patterned metal layer over the substrate, the patterned metal layer having a bottom surface facing the substrate; forming an insulator layer over the patterned metal layer, the insulator layer having a bottom surface facing the substrate; forming a second metal layer over the insulator layer; removing part of the insulator layer and part of the second metal layer thereby forming a substantially coplanar surface that is formed by the patterned metal layer, the insulator layer, and the second metal layer, wherein after removing part of the insulator layer and part of the second metal layer at least a portion of the bottom surface of the insulator layer is substantially coplanar with at least a portion of the bottom surface of the patterned metal layer; removing a portion of the second metal layer and a portion of the patterned metal layer to form a fin from the insulator layer that protrudes beyond the patterned metal layer and the second metal layer; forming an etch stop layer directly on a top surface of the fin, the top surface of the fin facing away from the substrate; and forming an inter-metal dielectric layer over the fin and the etch stop layer disposed directly on the top surface of the fin.
A method for making a metal-insulator-metal (MIM) capacitor involves depositing a patterned metal layer on a substrate. An insulator layer is then deposited over the patterned metal layer. A second metal layer is deposited over the insulator layer. Parts of the insulator and second metal layers are removed to create a coplanar surface with the patterned metal layer, where the bottom surfaces of the insulator and patterned metal layers are also coplanar. The second metal layer and patterned metal layer are etched to form a fin from the insulator layer that extends beyond the metal layers. An etch stop layer is formed directly on top of the fin, and an inter-metal dielectric layer is formed over the fin and etch stop layer.
9. The method of claim 8 , further comprising forming a first via and a second via through the inter-metal dielectric layer so as to communicate the patterned metal layer and the second metal layer respectively.
The MIM capacitor fabrication method described previously, involving a patterned metal layer and an insulator layer deposited on a substrate, followed by a second metal layer, planarization to create a coplanar surface, etching to create an insulator fin with an etch stop layer, and formation of a dielectric layer on top, includes forming vias through the inter-metal dielectric layer to connect to the patterned and second metal layers.
10. The method of claim 8 , wherein removing part of the insulator layer and part of the second metal layer includes performing a chemical-mechanical planarization (CMP) process.
This invention relates to semiconductor manufacturing, specifically to a method for fabricating integrated circuits with improved electrical isolation. The problem addressed is the need for precise removal of excess conductive and insulating materials during the formation of interconnect structures, ensuring reliable device performance while minimizing defects. The method involves depositing an insulator layer over a substrate, followed by a second metal layer. To form conductive features, part of the insulator layer and part of the second metal layer are selectively removed. This removal process is performed using chemical-mechanical planarization (CMP), which combines chemical etching with mechanical polishing to achieve a smooth, planar surface. CMP ensures uniform removal of material, reducing defects and improving the integrity of the resulting interconnect structures. The method may also include forming a first metal layer on the substrate before depositing the insulator layer, where the first metal layer serves as a conductive base for the interconnects. The insulator layer electrically isolates the metal layers, preventing short circuits. The CMP process is carefully controlled to avoid over-etching or under-etching, ensuring precise feature dimensions and reliable electrical connections. This approach enhances manufacturing yield and device reliability by minimizing imperfections in the interconnect structures, which are critical for high-performance semiconductor devices. The use of CMP provides a cost-effective and scalable solution for advanced semiconductor fabrication.
11. The method of claim 8 , wherein removing the portion of the second metal layer and the portion of the patterned metal layer includes performing a wet etching process.
The MIM capacitor fabrication method described previously, involving a patterned metal layer and an insulator layer deposited on a substrate, followed by a second metal layer, planarization to create a coplanar surface, etching to create an insulator fin with an etch stop layer, and formation of a dielectric layer on top, uses a wet etching process to remove parts of the second metal and patterned metal layers to form the insulator fin.
12. The method of claim 11 , wherein the wet etching process includes applying standard clean 1 (SC1) onto the substrate at temperature ranging from about 15° C. to about 80° C.
The MIM capacitor fabrication method described previously, involving a patterned metal layer and an insulator layer deposited on a substrate, followed by a second metal layer, planarization to create a coplanar surface, etching to create an insulator fin with an etch stop layer, and formation of a dielectric layer on top, performs a wet etch using Standard Clean 1 (SC1) at a temperature between 15°C and 80°C to remove parts of the second metal and patterned metal layers, creating the insulator fin.
13. The method of claim 8 , wherein, from a top view, the patterned metal layer, the insulator layer, and the second metal layer form concentric circles.
The MIM capacitor fabrication method described previously, involving a patterned metal layer and an insulator layer deposited on a substrate, followed by a second metal layer, planarization to create a coplanar surface, etching to create an insulator fin with an etch stop layer, and formation of a dielectric layer on top, features a layout where the patterned metal, insulator, and second metal layers are concentric circles when viewed from above.
14. The method of claim 8 , wherein, from a top view, each of the patterned metal layer, the insulator layer, and the second metal layer forms form a polygon shape with rounded corners.
The MIM capacitor fabrication method described previously, involving a patterned metal layer and an insulator layer deposited on a substrate, followed by a second metal layer, planarization to create a coplanar surface, etching to create an insulator fin with an etch stop layer, and formation of a dielectric layer on top, features metal and insulator layers shaped as polygons with rounded corners when viewed from above.
15. The method of claim 8 , wherein after removing the portion of the second metal layer and the portion of the patterned metal layer to form the fin from the insulator layer, the patterned metal layer has a top surface that is substantially coplanar with a top surface of the second metal layer such that the fin protrudes beyond the top surface of the patterned metal layer and the top surface of the second metal layer.
The MIM capacitor fabrication method described previously, involving a patterned metal layer and an insulator layer deposited on a substrate, followed by a second metal layer, planarization to create a coplanar surface, etching to create an insulator fin with an etch stop layer, and formation of a dielectric layer on top, results in the top surfaces of the patterned metal layer and the second metal layer being coplanar after etching, allowing the insulator fin to protrude above the metal layers.
16. A method comprising: forming a first metal layer over a substrate; forming an insulating layer over the first metal layer and directly on the substrate such that the insulating layer physically contacts the substrate; forming a second metal layer over the insulator layer; planarizing the first metal layer, the insulating layer, and the second metal layer such that top surfaces of the first metal layer, the insulating layer, and the second metal layer are substantially coplanar; after planarizing the first metal layer, the insulating layer, and the second metal layer, removing a portion of the first metal layer and a portion of the second metal layer to expose opposing sidewall surfaces of the insulating layer; and forming a dielectric layer on the exposed opposing sidewall surfaces of the insulating layer.
A method for making a metal-insulator-metal (MIM) capacitor includes depositing a first metal layer on a substrate, followed by an insulating layer that directly contacts the substrate. A second metal layer is deposited over the insulator layer. The metal and insulator layers are planarized, resulting in coplanar top surfaces. Portions of the first and second metal layers are then removed, exposing sidewalls of the insulator layer. Finally, a dielectric layer is formed on these exposed sidewall surfaces.
17. The method of claim 16 , further comprising forming a first trench through the dielectric layer to the first metal layer and forming a second trench through the dielectric to the second metal layer, and wherein the first trench and the second trench have substantially the same depth.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate, and a second metal layer, planarized to coplanar surfaces, metal etched to expose insulator sidewalls, and a dielectric formed on those sidewalls, involves etching trenches through the dielectric layer to reach each metal layer. These trenches connecting to the first and second metal layers have the same depth.
18. The method of claim 17 , further comprising forming a conductive material within the first trench and the second trench.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate, and a second metal layer, planarized to coplanar surfaces, metal etched to expose insulator sidewalls, a dielectric formed on those sidewalls, and trenches etched to the metal layers, includes filling those trenches with a conductive material.
19. The method of claim 16 , wherein planarizing the first metal layer, the insulating layer, and the second metal layer includes performing an etching process.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate, and a second metal layer, planarized to coplanar surfaces, metal etched to expose insulator sidewalls, and a dielectric formed on those sidewalls, utilizes an etching process for planarizing the metal and insulator layers.
20. The method of claim 16 , wherein the substrate is formed of a dielectric material.
The MIM capacitor fabrication method described previously, where a first metal layer is deposited on a substrate, followed by an insulator layer that directly contacts the substrate, and a second metal layer, planarized to coplanar surfaces, metal etched to expose insulator sidewalls, and a dielectric formed on those sidewalls, uses a substrate made of a dielectric material.
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September 8, 2015
May 30, 2017
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