An analog-digital converting device includes a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal, a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, and a combining circuit suitable for combining the upper N-bits and the lower M-bits.
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1. An analog-digital converting device, comprising: a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal using a predetermined SAR logic; a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal using a predetermined SS logic that is different from the predetermined SAR logic; and a combining circuit suitable for combining the upper N-bits and the lower M-bits to provide an output signal having (N+M) bits, M and N being positive integers, wherein the SAR analog-digital converting circuit using the predetermined SAR logic is different from the SS analog-digital converting circuit using the predetermined SS logic.
An analog-to-digital converter (ADC) has two main parts: a Successive Approximation Register (SAR) ADC and a Single-Slope (SS) ADC. The SAR ADC handles the most significant N bits of the input signal using SAR logic. Then, the SS ADC handles the least significant M bits of the same input signal using SS logic, which is different from the SAR logic. A combining circuit then merges the N and M bits to create a digital output signal with a total resolution of (N+M) bits. These positive integers N and M define the resolution split between the two ADC types within this hybrid converter.
2. The analog-digital converting device of claim 1 , wherein the SS analog-digital converting circuit resolves the lower M-bits using a remaining voltage of the input signal after the SAR analog-digital converting circuit resolves the upper N-bits.
The analog-to-digital converter as described previously (an ADC has a Successive Approximation Register (SAR) ADC handling the most significant N bits, and a Single-Slope (SS) ADC handling the least significant M bits, with a combining circuit) operates such that the SS ADC converts the residual voltage remaining *after* the SAR ADC has completed its conversion of the upper N bits. The SS ADC processes this remaining voltage to determine the lower M bits of the digital representation.
3. The analog-digital converting device of claim 1 , wherein the SAR analog-digital converting circuit comprises: a capacitor digital-analog converting unit suitable for selecting one of a first reference voltage and a second reference voltage based on a comparison result of a comparator; the comparator suitable for comparing an output voltage of the capacitor digital-analog converting unit with the second reference voltage; and a memory unit suitable for storing the comparison result of the comparator.
The Successive Approximation Register (SAR) ADC portion of the analog-to-digital converter (an ADC has a Successive Approximation Register (SAR) ADC handling the most significant N bits, and a Single-Slope (SS) ADC handling the least significant M bits, with a combining circuit) contains a capacitor-based digital-to-analog converter (DAC). This DAC selects either a first or second reference voltage depending on the output of a comparator. The comparator compares the DAC's output voltage to the second reference voltage. The result of this comparison is then stored in a memory unit.
4. The analog-digital converting device of claim 3 , wherein the capacitor digital-analog converting unit outputs a remaining voltage of the input signal after the SAR analog-digital converting circuit completes a resolution operation to provide the upper N-bits.
Building on the previous description of the SAR ADC (a capacitor-based DAC selecting between two reference voltages based on comparator output stored in memory), after the SAR ADC finishes converting the upper N bits of the input signal, the capacitor-based DAC outputs the remaining voltage of the original input signal. This remaining voltage is then used by the Single-Slope ADC to determine the lower M bits. The DAC provides this residual as the starting point for the subsequent single-slope conversion.
5. The analog-digital converting device of claim 1 , wherein the SS analog-digital converting circuit comprises: a ramp signal generator suitable for generating a ramp signal, which is synchronized with a clock signal; a capacitor digital-analog converting unit suitable for outputting a voltage changing from a remaining voltage of the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, based on the ramp signal; a comparator suitable for comparing an output voltage of the capacitor digital-analog converting unit with the second reference voltage; and a counter suitable for counting the number of clock cycles of the clock signal until a logic value of a comparison result of the comparator is changed.
The Single-Slope (SS) ADC portion of the analog-to-digital converter (an ADC has a Successive Approximation Register (SAR) ADC handling the most significant N bits, and a Single-Slope (SS) ADC handling the least significant M bits, with a combining circuit) includes a ramp signal generator that creates a ramp signal synchronized with a clock signal. It also includes a capacitor-based digital-to-analog converter (DAC) that outputs a voltage based on the ramp signal, starting from the remaining voltage of the input signal (after the SAR ADC has converted the upper N bits). A comparator then compares this DAC output to a second reference voltage. A counter tracks the number of clock cycles until the comparator output changes its logic state.
6. The analog-digital converting device of claim 5 , wherein an output terminal of the ramp signal generator is coupled to a sampling capacitor of a capacitor digital-analog converting unit of the SAR analog-digital converting circuit.
In the analog-to-digital converter using both SAR and Single-Slope ADCs, as previously described, specifically the Single-Slope ADC having a ramp generator, DAC, comparator, and counter, the output of the ramp signal generator is directly connected to a sampling capacitor within the capacitor-based DAC of the Successive Approximation Register (SAR) ADC circuit. This connection allows the ramp signal to influence the voltage on the sampling capacitor during the single-slope conversion.
7. The analog-digital converting device of claim 6 , wherein the ramp signal generator provides the ramp signal, which has a plurality of steps and a step size of (second reference voltage−first reference voltage)/2 M , to the sampling capacitor.
Continuing from the description of the shared ramp signal, where the ramp signal generator's output connects to the sampling capacitor of the SAR ADC's DAC, the ramp signal isn't a smooth, continuous slope. Instead, it's a stepped ramp, with a plurality of discrete voltage steps. Each step has a size of (second reference voltage - first reference voltage) / 2<sup>M</sup>, where M is the number of bits resolved by the single-slope ADC. This stepped ramp allows for precise control over the single-slope conversion process.
8. The analog-digital converting device of claim 1 , wherein the SAR analog-digital converting circuit shares a capacitor digital-analog converting unit and a comparator with the SS analog-digital converting circuit.
The analog-to-digital converter design with SAR and Single-Slope ADCs saves hardware by having the SAR and SS ADCs share both the capacitor-based digital-to-analog converter (DAC) and the comparator circuits. This means that the same DAC and comparator are used for both the successive approximation and the single-slope conversion processes, reducing the overall component count and potentially the size and cost of the device.
9. An analog-digital converting method, comprising: resolving upper N-bits for an input signal using a successive approximation register (SAR) analog-digital converting circuit having a predetermined SAR logic; resolving lower M-bits for the input signal using a single-slope (SS) analog-digital converting circuit having a predetermined SS logic that is different from the predetermined SAR logic; and combining the upper N-bits and the lower M-bits to provide an output signal having (N+M) bits, wherein the SAR analog-digital converting circuit having the predetermined SAR logic is different from the SS analog-digital converting circuit having the predetermined SS logic.
An analog-to-digital conversion method involves first using a Successive Approximation Register (SAR) ADC to determine the most significant N bits of an input signal, applying a specific SAR logic. Then, a Single-Slope (SS) ADC is used to determine the least significant M bits of the same input signal, using a different SS logic. Finally, the N and M bits are combined to form a complete (N+M)-bit digital output signal. The SAR and SS logic operations are distinct.
10. The analog-digital converting method of claim 9 , wherein the resolving of the lower M-bits includes resolving the lower M-bits using a remaining voltage of the input signal after the SAR analog-digital converting circuit resolves the upper N-bits.
The analog-to-digital conversion method described previously (using a Successive Approximation Register (SAR) ADC for the upper N bits and a Single-Slope (SS) ADC for the lower M bits) specifically uses the remaining voltage of the input signal, after the SAR ADC has finished its conversion of the upper N bits, as the starting point for the Single-Slope ADC to resolve the lower M bits.
11. The analog-digital converting method of claim 9 , wherein the resolving of the lower M-bits includes providing a ramp signal generated from a ramp signal generator to a sampling capacitor of a capacitor digital-analog converting unit of the SAR analog-digital converting circuit.
The analog-to-digital conversion method using both SAR and Single-Slope ADCs involves providing a ramp signal, generated by a ramp signal generator, to a sampling capacitor within a capacitor-based digital-to-analog converter (DAC) that's part of the SAR ADC. This ramp signal is used during the single-slope conversion process to determine the lower M bits of the input signal.
12. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising: a pixel array suitable for generating a pixel signal; a successive approximation register (SAR) and single-slope (SS) analog-digital converting device suitable for resolving upper N-bits for the pixel signal using an SAR analog-digital converting circuit having a predetermined SAR logic, resolving lower M-bits for the pixel signal using an SS analog-digital converting circuit having a predetermined SS logic that is different from the predetermined SAR logic, and combining the upper N-bits and the lower M-bits to provide a digital pixel signal having (N+M) bits; and an image signal processing circuit suitable for performing image processing on the digital pixel signal output from the SAR and SS analog-digital converting device, wherein the SAR analog-digital converting circuit having the predetermined SAR logic is different from the SS analog-digital converting circuit having the predetermined SS logic.
A CMOS image sensor contains a pixel array that generates pixel signals. These signals are then converted to digital form by a hybrid ADC. This ADC first resolves the upper N bits of the pixel signal using a Successive Approximation Register (SAR) ADC with SAR logic. Next, it resolves the lower M bits using a Single-Slope (SS) ADC with different SS logic. The resulting N and M bits are combined to produce a digital pixel signal with (N+M) bits. This digital signal is then processed by an image signal processing circuit. The SAR and SS logic operations are distinct.
13. The CMOS image sensor of claim 12 , wherein the SS analog-digital converting circuit resolves the lower M-bits using a remaining voltage of the pixel signal after the SAR analog-digital converting circuit resolves the upper M-bits.
The CMOS image sensor described previously (with a pixel array, hybrid SAR/SS ADC, and image signal processor) uses the remaining voltage of the pixel signal, after the Successive Approximation Register (SAR) ADC has finished converting the upper N bits, as the starting point for the Single-Slope (SS) ADC to resolve the lower M bits.
14. The CMOS image sensor of claim 12 , wherein the SAR analog-digital converting circuit comprises: a capacitor digital-analog converting unit suitable for selecting one of a first reference voltage and a second reference voltage based on a comparison result of a comparator; the comparator suitable for comparing an output voltage of the capacitor digital-analog converting unit with the second reference voltage; and a memory unit suitable for storing the comparison result of the comparator.
In the CMOS image sensor with the SAR/SS hybrid ADC, the Successive Approximation Register (SAR) ADC part contains a capacitor-based digital-to-analog converter (DAC). This DAC selects either a first or second reference voltage based on the output of a comparator. The comparator compares the DAC's output voltage to the second reference voltage. The result of this comparison is then stored in a memory unit.
15. The CMOS image sensor of claim 12 , wherein the SS analog-digital converting circuit comprises: a ramp signal generator suitable for generating a ramp signal, which is synchronized with a clock signal; a capacitor digital-analog converting unit suitable for outputting a voltage changing from a remaining voltage of the pixel signal after the SAR analog-digital converting circuit resolves the upper N-bits, based on the ramp signal; a comparator suitable for comparing an output voltage of the capacitor digital-analog converting unit with a second reference voltage; and a counter suitable for counting the number of clock cycles of the clock signal until a logic value of a comparison result of the comparator is changed.
The Single-Slope (SS) ADC portion within the CMOS image sensor with the hybrid SAR/SS ADC includes a ramp signal generator that creates a ramp signal synchronized with a clock signal. It also has a capacitor-based digital-to-analog converter (DAC) that outputs a voltage based on the ramp signal, starting from the remaining voltage of the pixel signal (after the SAR ADC has converted the upper N bits). A comparator compares this DAC output to a second reference voltage. A counter tracks the number of clock cycles until the comparator output changes its logic state.
16. The CMOS image sensor of claim 15 , wherein an output terminal of the ramp signal generator is coupled to a sampling capacitor of a capacitor digital-analog converting unit of the SAR analog-digital converting circuit.
In the CMOS image sensor with a hybrid SAR/SS ADC, with the Single-Slope ADC having a ramp generator, DAC, comparator, and counter, the output of the ramp signal generator is directly connected to a sampling capacitor within the capacitor-based DAC of the Successive Approximation Register (SAR) ADC circuit. This connection allows the ramp signal to influence the voltage on the sampling capacitor during the single-slope conversion.
17. An analog-digital converting device, comprising: a single-slope (SS) analog-digital converting circuit suitable for resolving upper N-bits for an input signal using a predetermined SS logic; a successive approximation register (SAR) analog-digital converting circuit suitable for resolving lower M-bits for the input signal using a predetermined SAR logic that is different from the predetermined SS logic; and a combining circuit suitable for combining the upper N-bits and the lower M-bits to provide an output signal having (N+M) bits, wherein the SAR analog-digital converting circuit using the predetermined SAR logic is different from the SS analog-digital converting circuit using the predetermined SS logic.
An analog-to-digital converter (ADC) inverts the order of conversion compared to previous claims. Here, a Single-Slope (SS) ADC handles the most significant N bits of the input signal using SS logic. Subsequently, a Successive Approximation Register (SAR) ADC handles the least significant M bits of the input signal using SAR logic, different from the SS logic. A combining circuit then merges the N and M bits to create a digital output signal with a total resolution of (N+M) bits. The distinct SS and SAR logic implementations are key.
18. The analog-digital converting device of 17 , wherein the SAR analog-digital converting circuit resolves the lower M-bits using a remaining voltage of the input signal after the SS analog-digital converting circuit resolves the upper N-bits.
The analog-to-digital converter, with the Single-Slope (SS) ADC converting the most significant N bits *before* the Successive Approximation Register (SAR) ADC converts the least significant M bits, operates such that the SAR ADC converts the residual voltage remaining *after* the SS ADC has completed its conversion of the upper N bits. The SAR ADC processes this remaining voltage to determine the lower M bits of the digital representation.
19. An analog-digital converting method, comprising: resolving upper N-bits for an input signal using a single-slope (SS) analog-digital converting circuit having a predetermined SS logic; resolving lower M-bits for the input signal using a successive approximation register (SAR) analog-digital converting circuit having a predetermined SAR logic that is different from the predetermined SS logic; and combining the upper N-bits and the lower M-bits to provide an output signal having (N+M) bits, wherein the SAR analog-digital converting circuit having the predetermined SAR logic is different from the SS analog-digital converting circuit having the predetermined SS logic.
An analog-to-digital conversion method involves using a Single-Slope (SS) ADC to determine the most significant N bits of an input signal, applying a specific SS logic. Then, a Successive Approximation Register (SAR) ADC is used to determine the least significant M bits of the same input signal, using a different SAR logic. Finally, the N and M bits are combined to form a complete (N+M)-bit digital output signal. The SAR and SS logic operations are distinct.
20. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising: a pixel array suitable for generating a pixel signal; a single-slope (SS) and successive approximation register (SAR) analog-digital converting device suitable for resolving upper N-bits for the pixel signal using an SS analog-digital converting circuit having a predetermined SS logic, resolving lower M-bits for the pixel signal using an SAR analog-digital converting circuit having a predetermined SAR logic that is different from the predetermined SS logic, and combining the upper N-bits and the lower M-bits to provide a digital pixel signal having (N+M) bits; and an image signal processing circuit suitable for performing image processing on the digital pixel signal output from the SS and SAR analog-digital converting device, wherein the SAR analog-digital converting circuit having the predetermined SAR logic is different from the SS analog-digital converting circuit having the predetermined SS logic.
A CMOS image sensor contains a pixel array that generates pixel signals. These signals are converted to digital form by a hybrid ADC, working in reverse order. This ADC first resolves the upper N bits of the pixel signal using a Single-Slope (SS) ADC with SS logic. Next, it resolves the lower M bits using a Successive Approximation Register (SAR) ADC with different SAR logic. The resulting N and M bits are combined to produce a digital pixel signal with (N+M) bits. This digital signal is then processed by an image signal processing circuit. The SAR and SS logic operations are distinct.
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November 17, 2014
May 30, 2017
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