An analog-digital converting device includes a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal, a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, and a combining circuit suitable for combining the upper N-bits and the lower M-bits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An analog-digital converting device, comprising: a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal using a predetermined SAR logic; a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal using a predetermined SS logic that is different from the predetermined SAR logic; and a combining circuit suitable for combining the upper N-bits and the lower M-bits to provide an output signal having (N+M) bits, M and N being positive integers, wherein the SAR analog-digital converting circuit using the predetermined SAR logic is different from the SS analog-digital converting circuit using the predetermined SS logic.
2. The analog-digital converting device of claim 1 , wherein the SS analog-digital converting circuit resolves the lower M-bits using a remaining voltage of the input signal after the SAR analog-digital converting circuit resolves the upper N-bits.
3. The analog-digital converting device of claim 1 , wherein the SAR analog-digital converting circuit comprises: a capacitor digital-analog converting unit suitable for selecting one of a first reference voltage and a second reference voltage based on a comparison result of a comparator; the comparator suitable for comparing an output voltage of the capacitor digital-analog converting unit with the second reference voltage; and a memory unit suitable for storing the comparison result of the comparator.
4. The analog-digital converting device of claim 3 , wherein the capacitor digital-analog converting unit outputs a remaining voltage of the input signal after the SAR analog-digital converting circuit completes a resolution operation to provide the upper N-bits.
5. The analog-digital converting device of claim 1 , wherein the SS analog-digital converting circuit comprises: a ramp signal generator suitable for generating a ramp signal, which is synchronized with a clock signal; a capacitor digital-analog converting unit suitable for outputting a voltage changing from a remaining voltage of the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, based on the ramp signal; a comparator suitable for comparing an output voltage of the capacitor digital-analog converting unit with the second reference voltage; and a counter suitable for counting the number of clock cycles of the clock signal until a logic value of a comparison result of the comparator is changed.
6. The analog-digital converting device of claim 5 , wherein an output terminal of the ramp signal generator is coupled to a sampling capacitor of a capacitor digital-analog converting unit of the SAR analog-digital converting circuit.
7. The analog-digital converting device of claim 6 , wherein the ramp signal generator provides the ramp signal, which has a plurality of steps and a step size of (second reference voltage−first reference voltage)/2 M , to the sampling capacitor.
8. The analog-digital converting device of claim 1 , wherein the SAR analog-digital converting circuit shares a capacitor digital-analog converting unit and a comparator with the SS analog-digital converting circuit.
9. An analog-digital converting method, comprising: resolving upper N-bits for an input signal using a successive approximation register (SAR) analog-digital converting circuit having a predetermined SAR logic; resolving lower M-bits for the input signal using a single-slope (SS) analog-digital converting circuit having a predetermined SS logic that is different from the predetermined SAR logic; and combining the upper N-bits and the lower M-bits to provide an output signal having (N+M) bits, wherein the SAR analog-digital converting circuit having the predetermined SAR logic is different from the SS analog-digital converting circuit having the predetermined SS logic.
10. The analog-digital converting method of claim 9 , wherein the resolving of the lower M-bits includes resolving the lower M-bits using a remaining voltage of the input signal after the SAR analog-digital converting circuit resolves the upper N-bits.
11. The analog-digital converting method of claim 9 , wherein the resolving of the lower M-bits includes providing a ramp signal generated from a ramp signal generator to a sampling capacitor of a capacitor digital-analog converting unit of the SAR analog-digital converting circuit.
12. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising: a pixel array suitable for generating a pixel signal; a successive approximation register (SAR) and single-slope (SS) analog-digital converting device suitable for resolving upper N-bits for the pixel signal using an SAR analog-digital converting circuit having a predetermined SAR logic, resolving lower M-bits for the pixel signal using an SS analog-digital converting circuit having a predetermined SS logic that is different from the predetermined SAR logic, and combining the upper N-bits and the lower M-bits to provide a digital pixel signal having (N+M) bits; and an image signal processing circuit suitable for performing image processing on the digital pixel signal output from the SAR and SS analog-digital converting device, wherein the SAR analog-digital converting circuit having the predetermined SAR logic is different from the SS analog-digital converting circuit having the predetermined SS logic.
13. The CMOS image sensor of claim 12 , wherein the SS analog-digital converting circuit resolves the lower M-bits using a remaining voltage of the pixel signal after the SAR analog-digital converting circuit resolves the upper M-bits.
14. The CMOS image sensor of claim 12 , wherein the SAR analog-digital converting circuit comprises: a capacitor digital-analog converting unit suitable for selecting one of a first reference voltage and a second reference voltage based on a comparison result of a comparator; the comparator suitable for comparing an output voltage of the capacitor digital-analog converting unit with the second reference voltage; and a memory unit suitable for storing the comparison result of the comparator.
15. The CMOS image sensor of claim 12 , wherein the SS analog-digital converting circuit comprises: a ramp signal generator suitable for generating a ramp signal, which is synchronized with a clock signal; a capacitor digital-analog converting unit suitable for outputting a voltage changing from a remaining voltage of the pixel signal after the SAR analog-digital converting circuit resolves the upper N-bits, based on the ramp signal; a comparator suitable for comparing an output voltage of the capacitor digital-analog converting unit with a second reference voltage; and a counter suitable for counting the number of clock cycles of the clock signal until a logic value of a comparison result of the comparator is changed.
16. The CMOS image sensor of claim 15 , wherein an output terminal of the ramp signal generator is coupled to a sampling capacitor of a capacitor digital-analog converting unit of the SAR analog-digital converting circuit.
17. An analog-digital converting device, comprising: a single-slope (SS) analog-digital converting circuit suitable for resolving upper N-bits for an input signal using a predetermined SS logic; a successive approximation register (SAR) analog-digital converting circuit suitable for resolving lower M-bits for the input signal using a predetermined SAR logic that is different from the predetermined SS logic; and a combining circuit suitable for combining the upper N-bits and the lower M-bits to provide an output signal having (N+M) bits, wherein the SAR analog-digital converting circuit using the predetermined SAR logic is different from the SS analog-digital converting circuit using the predetermined SS logic.
18. The analog-digital converting device of 17 , wherein the SAR analog-digital converting circuit resolves the lower M-bits using a remaining voltage of the input signal after the SS analog-digital converting circuit resolves the upper N-bits.
19. An analog-digital converting method, comprising: resolving upper N-bits for an input signal using a single-slope (SS) analog-digital converting circuit having a predetermined SS logic; resolving lower M-bits for the input signal using a successive approximation register (SAR) analog-digital converting circuit having a predetermined SAR logic that is different from the predetermined SS logic; and combining the upper N-bits and the lower M-bits to provide an output signal having (N+M) bits, wherein the SAR analog-digital converting circuit having the predetermined SAR logic is different from the SS analog-digital converting circuit having the predetermined SS logic.
20. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising: a pixel array suitable for generating a pixel signal; a single-slope (SS) and successive approximation register (SAR) analog-digital converting device suitable for resolving upper N-bits for the pixel signal using an SS analog-digital converting circuit having a predetermined SS logic, resolving lower M-bits for the pixel signal using an SAR analog-digital converting circuit having a predetermined SAR logic that is different from the predetermined SS logic, and combining the upper N-bits and the lower M-bits to provide a digital pixel signal having (N+M) bits; and an image signal processing circuit suitable for performing image processing on the digital pixel signal output from the SS and SAR analog-digital converting device, wherein the SAR analog-digital converting circuit having the predetermined SAR logic is different from the SS analog-digital converting circuit having the predetermined SS logic.
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November 17, 2014
May 30, 2017
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