A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provides instruction processing flexibility. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of processing instructions of multiple instruction streams in a processor core having a plurality of instruction execution slices, the method comprising: analyzing the multiple instruction streams and detecting, in a first one of the multiple instruction streams, an event indicating that a first instruction requires processing that changes resource availability for execution of a subsequent instruction of the first instruction stream or that the subsequent instruction has execution requirements such that a change in mapping between the instruction execution slices and corresponding ones of the multiple instruction streams is indicated, wherein the subsequent instruction is an instruction having a width greater than a width of each of the plurality of instruction execution slices; and responsive to detecting the event, modifying the first one of the multiple instruction streams by inserting a directive in the first one of the multiple instruction streams, wherein the directive, when executed by the another processor core will cause the change in mapping so that at least a portion of the subsequent instruction is dispatched to a selected one of the instruction execution slices that was assigned to a second one of the multiple instruction streams during a previous execution cycle, wherein the dispatching dispatches a first portion of the subsequent instruction to the selected instruction execution slice and a second portion of the subsequent instruction to another instruction execution slice that executed an instruction previous to the first instruction for the first instruction stream, wherein the event is an SIMD instruction and wherein the dispatching dispatches the subsequent instruction to the selected instruction execution slice and another instruction execution slice that executed an instruction previous to the first instruction for the first instruction stream, wherein the selected instruction execution slice and the another instruction execution slice process different data associated with the SIMD instruction.
The processor core handles multiple instruction streams using parallel execution slices. It analyzes these streams and detects an "event" in the first stream, signaling either a resource change required by a first instruction impacting a subsequent instruction, or that the subsequent instruction (wider than a single slice) needs a different slice mapping. If this event is detected, the compiler inserts a directive. This directive, when executed, remaps the instruction slices, dispatching part of the subsequent instruction to a selected slice previously assigned to a second instruction stream, and another part to a slice that handled a prior instruction in the first stream. If the "event" is a SIMD instruction, the subsequent instruction is dispatched to the selected slice and a slice that executed a previous instruction for the first stream, so that the selected slice and the other slice process different data associated with the SIMD instruction.
2. The method of claim 1 , wherein the detecting an event detects that another instruction execution slice that executed an instruction previous to the first instruction for the first instruction stream is unavailable.
This builds upon the previous description of a processor core handling multiple instruction streams using parallel execution slices. Besides detecting resource requirements or wide instructions, the "event" detected is specifically that another instruction execution slice that previously executed an instruction of the first instruction stream is now unavailable. The processor detects that the slice that should be processing is busy or otherwise unable to process the instruction.
3. The method of claim 1 , further comprising, by a compiler that generates program code of the multiple instruction streams, inserting a directive in the program code to control the dispatching, wherein the detecting detects the directive in the program code, and wherein the dispatching is performed responsive to detecting the directive.
Expanding on the method of processing multiple instruction streams using parallel slices, a compiler generating the program code inserts a directive into the code to manage how instructions are dispatched to the execution slices. The system detects this compiler-inserted directive. The dispatching of instructions to different slices is then directly controlled by the presence of this directive in the code.
4. The method of claim 1 , further comprising, by a scheduler that pre-processes program code of the multiple instruction streams to allocate resources to hardware threads corresponding to the multiple instruction streams, inserting a directive in the program code to control the dispatching, wherein the detecting detects the directive in the program code, and wherein the dispatching is performed responsive to detecting the directive.
Extending the previous method of processing multiple instruction streams using parallel slices, a scheduler pre-processes the program code and inserts directives to control instruction dispatching. This scheduler allocates resources to hardware threads corresponding to the streams. The system then detects these scheduler-inserted directives. Instruction dispatching is then performed according to these directives that the scheduler added to the program code.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 12, 2014
June 27, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.