A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A three-dimensional chip stack, comprising: a first chip comprising a first substrate; and a second chip comprising a second substrate; wherein the first chip is bonded to the second chip to form a bonded interconnection between the first substrate and the second substrate, wherein the bonded interconnection comprises a first conductive pillar overlying the first substrate, a second conductive pillar overlying the second substrate, and a joint structure between the first conductive pillar and the second conductive pillar; and wherein the joint structure comprises a first intermetallic compound (IMC) region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.
2. The three-dimensional chip stack of claim 1 , wherein the metallization layer comprises a copper layer.
3. The three-dimensional chip stack o of claim 1 , wherein the first IMC region comprises copper and tin.
4. The three-dimensional chip stack of claim 1 , wherein the second IMC region comprises copper and tin.
5. The three-dimensional chip stack of claim 1 , wherein the first conductive pillar comprises a copper pillar.
6. The three-dimensional chip stack of claim 5 , wherein the first conductive pillar comprises a metal capping layer on the copper pillar.
7. The three-dimensional chip stack of claim 6 , wherein the metal capping layer comprises a nickel layer.
8. The three-dimensional chip stack o of claim 7 , wherein the first IMC region comprises copper, tin and nickel.
9. The three-dimensional chip stack of claim 1 , wherein the second conductive pillar comprises a copper pillar.
10. The three-dimensional chip stack of claim 9 , wherein the second conductive pillar comprises a metal capping layer on the copper pillar.
11. The three-dimensional chip stack of claim 10 , wherein the metal capping layer comprises a nickel layer.
12. The three-dimensional chip stack o of claim 11 , wherein the second IMC region comprises copper, tin and nickel.
13. A method of forming a three-dimensional chip stack, comprising: forming a first bump structure on a first semiconductor substrate, wherein the first bump structure comprises a first conductive pillar and a first solder layer on top of the first conductive pillar; forming a second bump structure on a second semiconductor substrate, wherein the second bump structure comprises a second conductive pillar, a second solder layer on top of the second conductive pillar, and a metallization layer on the second solder layer; attaching the first bump structure to the second bump structure; and performing a thermal reflow process to form a first intermetallic compound (IMC) region between the first conductive pillar and the metallization layer, and a second IMC region between the second conductive pillar and the metallization layer.
14. The method of claim 13 , wherein the metallization layer comprises a copper layer, and the first IMC region comprises copper and tin.
15. The method of claim 13 , wherein the first conductive pillar comprises a copper pillar.
16. The method of claim 15 , wherein the first conductive pillar comprises a metal capping layer between the copper pillar and the first solder layer.
17. The method of claim 16 , wherein the metal capping layer comprises a nickel layer.
18. The method of claim 13 , wherein further comprising forming the first solder layer as a hemisphere-shaped solder layer before attaching the first bump structure to the second bump structure.
19. A method of forming a three-dimensional chip stack, comprising: receiving a first chip comprising a first bump structure formed on a first semiconductor substrate, wherein the first bump structure comprises a first conductive pillar and a first solder layer on top of the first conductive pillar; receiving a second chip comprising a second bump structure on a second semiconductor substrate, wherein the second bump structure comprises a second conductive pillar, a second solder layer on top of the second conductive pillar, and a metallization layer on the second solder layer; and bonding the first chip to the second chip by attaching the first bump structure to the second bump structure; wherein a first intermetallic compound (IMC) region comprising copper and tin is formed between the first conductive pillar and the metallization layer, and a second IMC region comprising copper and tin is formed between the second conductive pillar and the metallization layer.
20. The method of claim 19 , wherein the metallization layer comprises a copper layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 27, 2016
July 4, 2017
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