A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A three-dimensional chip stack, comprising: a first chip comprising a first substrate; and a second chip comprising a second substrate; wherein the first chip is bonded to the second chip to form a bonded interconnection between the first substrate and the second substrate, wherein the bonded interconnection comprises a first conductive pillar overlying the first substrate, a second conductive pillar overlying the second substrate, and a joint structure between the first conductive pillar and the second conductive pillar; and wherein the joint structure comprises a first intermetallic compound (IMC) region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.
A 3D chip stack has two chips connected. The first chip has a substrate, and the second chip has a substrate. They are bonded to create an electrical connection. This connection includes a conductive pillar on each substrate and a joint structure in between. The joint structure has two intermetallic compound (IMC) regions, one next to each pillar, with a metal layer sandwiched in the middle.
2. The three-dimensional chip stack of claim 1 , wherein the metallization layer comprises a copper layer.
The 3D chip stack is constructed from two bonded chips using pillars. A joint structure connects the pillars from each chip. The metallization layer in the joint structure, which connects the intermetallic compound (IMC) regions, is made of copper.
3. The three-dimensional chip stack o of claim 1 , wherein the first IMC region comprises copper and tin.
In the 3D chip stack using bonded chips with pillars, the joint structure connecting the pillars uses intermetallic compounds. The first intermetallic compound (IMC) region, which is adjacent to the first conductive pillar, is made of copper and tin.
4. The three-dimensional chip stack of claim 1 , wherein the second IMC region comprises copper and tin.
In the 3D chip stack using bonded chips with pillars, the joint structure connecting the pillars uses intermetallic compounds. The second intermetallic compound (IMC) region, which is adjacent to the second conductive pillar, is made of copper and tin.
5. The three-dimensional chip stack of claim 1 , wherein the first conductive pillar comprises a copper pillar.
The 3D chip stack connects two chips with pillars and a joint structure. The first conductive pillar, which sits on the first substrate, is a copper pillar.
6. The three-dimensional chip stack of claim 5 , wherein the first conductive pillar comprises a metal capping layer on the copper pillar.
The 3D chip stack connects two chips with pillars and a joint structure. The first conductive pillar is a copper pillar with a metal capping layer on top of the copper.
7. The three-dimensional chip stack of claim 6 , wherein the metal capping layer comprises a nickel layer.
The 3D chip stack connects two chips with pillars and a joint structure. The first conductive pillar is a copper pillar, and the metal capping layer on the copper pillar is a nickel layer.
8. The three-dimensional chip stack o of claim 7 , wherein the first IMC region comprises copper, tin and nickel.
In the 3D chip stack using bonded chips with pillars, the joint structure connecting the pillars uses intermetallic compounds. The first intermetallic compound (IMC) region, which is adjacent to a copper pillar with a nickel capping layer, is made of copper, tin, and nickel.
9. The three-dimensional chip stack of claim 1 , wherein the second conductive pillar comprises a copper pillar.
The 3D chip stack connects two chips with pillars and a joint structure. The second conductive pillar, which sits on the second substrate, is a copper pillar.
10. The three-dimensional chip stack of claim 9 , wherein the second conductive pillar comprises a metal capping layer on the copper pillar.
The 3D chip stack connects two chips with pillars and a joint structure. The second conductive pillar is a copper pillar with a metal capping layer on top of the copper.
11. The three-dimensional chip stack of claim 10 , wherein the metal capping layer comprises a nickel layer.
The 3D chip stack connects two chips with pillars and a joint structure. The second conductive pillar is a copper pillar, and the metal capping layer on the copper pillar is a nickel layer.
12. The three-dimensional chip stack o of claim 11 , wherein the second IMC region comprises copper, tin and nickel.
In the 3D chip stack using bonded chips with pillars, the joint structure connecting the pillars uses intermetallic compounds. The second intermetallic compound (IMC) region, which is adjacent to a copper pillar with a nickel capping layer, is made of copper, tin, and nickel.
13. A method of forming a three-dimensional chip stack, comprising: forming a first bump structure on a first semiconductor substrate, wherein the first bump structure comprises a first conductive pillar and a first solder layer on top of the first conductive pillar; forming a second bump structure on a second semiconductor substrate, wherein the second bump structure comprises a second conductive pillar, a second solder layer on top of the second conductive pillar, and a metallization layer on the second solder layer; attaching the first bump structure to the second bump structure; and performing a thermal reflow process to form a first intermetallic compound (IMC) region between the first conductive pillar and the metallization layer, and a second IMC region between the second conductive pillar and the metallization layer.
This invention relates to semiconductor packaging, specifically methods for forming three-dimensional chip stacks with improved electrical and mechanical connections. The problem addressed is the reliability and performance of interconnections in stacked semiconductor devices, particularly the formation of intermetallic compounds (IMCs) that can affect conductivity and structural integrity. The method involves forming bump structures on two semiconductor substrates. The first substrate has a bump structure with a conductive pillar topped by a solder layer. The second substrate has a bump structure with a conductive pillar, a solder layer, and an additional metallization layer on top of the solder. The bump structures are aligned and attached, followed by a thermal reflow process. This process creates two distinct IMC regions: one between the first substrate's conductive pillar and the metallization layer of the second substrate, and another between the second substrate's conductive pillar and its own metallization layer. The metallization layer enhances the formation of stable IMCs, improving electrical conductivity and mechanical strength in the stacked structure. This approach ensures robust interconnections while maintaining precise alignment and minimizing defects in the final three-dimensional chip stack.
14. The method of claim 13 , wherein the metallization layer comprises a copper layer, and the first IMC region comprises copper and tin.
In the method of creating a 3D chip stack by attaching bump structures with pillars and solder, followed by thermal reflow, the metallization layer on the second bump structure is copper. As a result, the first intermetallic compound (IMC) region formed between the first pillar and the copper layer contains copper and tin.
15. The method of claim 13 , wherein the first conductive pillar comprises a copper pillar.
In the method of creating a 3D chip stack by attaching bump structures with pillars and solder, followed by thermal reflow, the first conductive pillar in the first bump structure is made of copper.
16. The method of claim 15 , wherein the first conductive pillar comprises a metal capping layer between the copper pillar and the first solder layer.
In the method of creating a 3D chip stack by attaching bump structures with pillars and solder, followed by thermal reflow, the first conductive pillar is copper and includes a metal capping layer placed between the copper pillar and the first solder layer.
17. The method of claim 16 , wherein the metal capping layer comprises a nickel layer.
In the method of creating a 3D chip stack by attaching bump structures with pillars and solder, followed by thermal reflow, the metal capping layer between the copper pillar and the first solder layer is made of nickel.
18. The method of claim 13 , wherein further comprising forming the first solder layer as a hemisphere-shaped solder layer before attaching the first bump structure to the second bump structure.
In the method of creating a 3D chip stack by attaching bump structures with pillars and solder, one step involves shaping the first solder layer into a hemisphere *before* attaching the bump structures together. This creates a more controlled solder joint.
19. A method of forming a three-dimensional chip stack, comprising: receiving a first chip comprising a first bump structure formed on a first semiconductor substrate, wherein the first bump structure comprises a first conductive pillar and a first solder layer on top of the first conductive pillar; receiving a second chip comprising a second bump structure on a second semiconductor substrate, wherein the second bump structure comprises a second conductive pillar, a second solder layer on top of the second conductive pillar, and a metallization layer on the second solder layer; and bonding the first chip to the second chip by attaching the first bump structure to the second bump structure; wherein a first intermetallic compound (IMC) region comprising copper and tin is formed between the first conductive pillar and the metallization layer, and a second IMC region comprising copper and tin is formed between the second conductive pillar and the metallization layer.
A method of creating a 3D chip stack involves taking two chips, each with a bump structure. The first chip's bump includes a conductive pillar and a solder layer. The second chip's bump has a conductive pillar, a solder layer, and a metallization layer. The chips are bonded by attaching the bump structures. The process creates a first intermetallic compound (IMC) region made of copper and tin between the first conductive pillar and the metallization layer, and a second IMC region also of copper and tin, between the second conductive pillar and the metallization layer.
20. The method of claim 19 , wherein the metallization layer comprises a copper layer.
In the method of creating a 3D chip stack by bonding pre-fabricated chips with bump structures, and forming copper-tin intermetallic compounds, the metallization layer on the second chip's bump structure is made of copper.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 27, 2016
July 4, 2017
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