An assignment control method including: assigning, by circuitry, a processor core among a plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identifying, by the circuitry, address information of memory area, with which the processor core assigned to the thread accesses, based on identification information identifying the processor core assigned to the thread and associating information stored in a storage unit, the associating information associating identification information of the plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing the process of the thread; and controlling, by the circuitry, the processor core assigned to the thread to access corresponding memory area using the identified address information.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An assignment control method comprising: assigning, by circuitry, a processor core among a plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identifying, by the circuitry, address information of a memory area, with which the processor core assigned to the thread accesses, based on identification information identifying the processor core assigned to the thread and association information stored in a memory, the association information associating identification information of the plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing a corresponding process of a corresponding thread; controlling, by the circuitry, the processor core assigned to the thread to access the memory area using the identified address information; deploying, by the circuitry, the address information of the memory area from a reserved register management area of the memory, in combination with register information of a first register from a register save area of the memory, to the first register; and controlling, by the circuitry, the processor core assigned to the thread to access the memory area by using the address information of the memory area stored in the first register.
2. The assignment control method according to claim 1 , further comprising: storing, by the circuitry, the address information of the memory area in a second register; and controlling, by the circuitry, the processor core assigned to the thread to acquire the address information of the memory area from the second register.
3. A system comprising: a memory configured to store association information associating identification information of a plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing a corresponding process of a corresponding thread; and circuitry configured to: assign a processor core among the plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identify address information of a memory area, with which the processor core assigned to the thread accesses, based on the association information stored in the memory; control the processor core assigned to the thread to access the memory area using the identified address information; deploy the address information of the memory area from a reserved register management area of the memory, in combination with register information of a first register from a register save area of the memory, to the first register; and control the processor core assigned to the thread to access the memory area by using the address information of the memory area stored in the first register.
4. The system according to claim 3 , wherein the circuitry is further configured to: store the address information of the memory area in a second register; and control the processor core assigned to the thread to acquire the address information of the memory area from the second register.
5. The system according to claim 3 , wherein the system further comprises the plurality of processor cores, and the circuitry is configured to assign a plurality of threads to the plurality of processor cores.
6. A non-transitory computer-readable medium storing therein a program that causes a computer to execute a process, the process comprising: assigning a processor core among a plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identifying address information of a memory area, with which the processor core assigned to the thread accesses, based on identification information identifying the processor core assigned to the thread and association information stored in a memory, the association information associating identification information of the plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing a corresponding process of a corresponding thread; controlling the processor core assigned to the thread to access the memory area using the identified address information; deploying the address information of the memory area from a reserved register management area of the memory, in combination with register information of a first register from a register save area of the memory, to the first register; and controlling the processor core assigned to the thread to access the memory area by using the address information of the memory area stored in the first register.
7. The non-transitory computer-readable medium according to claim 6 , wherein the process further comprises: storing the address information of the memory area in a second register; and controlling the processor core assigned to the thread to acquire the address information of the memory area from the second register.
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August 11, 2015
July 11, 2017
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