An assignment control method including: assigning, by circuitry, a processor core among a plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identifying, by the circuitry, address information of memory area, with which the processor core assigned to the thread accesses, based on identification information identifying the processor core assigned to the thread and associating information stored in a storage unit, the associating information associating identification information of the plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing the process of the thread; and controlling, by the circuitry, the processor core assigned to the thread to access corresponding memory area using the identified address information.
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1. An assignment control method comprising: assigning, by circuitry, a processor core among a plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identifying, by the circuitry, address information of a memory area, with which the processor core assigned to the thread accesses, based on identification information identifying the processor core assigned to the thread and association information stored in a memory, the association information associating identification information of the plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing a corresponding process of a corresponding thread; controlling, by the circuitry, the processor core assigned to the thread to access the memory area using the identified address information; deploying, by the circuitry, the address information of the memory area from a reserved register management area of the memory, in combination with register information of a first register from a register save area of the memory, to the first register; and controlling, by the circuitry, the processor core assigned to the thread to access the memory area by using the address information of the memory area stored in the first register.
A method for managing threads on a multi-core processor involves assigning a processor core to a new thread when the process for that thread starts. The system identifies the memory area the assigned core should use by looking up the core's ID in a memory-resident table that links core IDs to specific memory regions. The assigned processor core then accesses this specific memory area. To facilitate this, the memory address of this memory area is loaded from a reserved memory region, combined with register information from a register save area, and placed into a general-purpose register. The processor core then uses this register to access its designated memory region.
2. The assignment control method according to claim 1 , further comprising: storing, by the circuitry, the address information of the memory area in a second register; and controlling, by the circuitry, the processor core assigned to the thread to acquire the address information of the memory area from the second register.
Building on the previous thread management description, this enhancement includes storing the memory area address in a dedicated register. Instead of directly using the general-purpose register, the processor core obtains the memory area address from this second, dedicated register. This facilitates quicker and more streamlined access to the designated memory location for the assigned thread.
3. A system comprising: a memory configured to store association information associating identification information of a plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing a corresponding process of a corresponding thread; and circuitry configured to: assign a processor core among the plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identify address information of a memory area, with which the processor core assigned to the thread accesses, based on the association information stored in the memory; control the processor core assigned to the thread to access the memory area using the identified address information; deploy the address information of the memory area from a reserved register management area of the memory, in combination with register information of a first register from a register save area of the memory, to the first register; and control the processor core assigned to the thread to access the memory area by using the address information of the memory area stored in the first register.
A system for managing threads on a multi-core processor includes a memory that stores a table linking processor core IDs to specific memory areas, and circuitry to manage thread assignments. The circuitry assigns a core to a new thread when its process starts. It then identifies the memory area the assigned core should use by looking up the core's ID in the memory resident table. The assigned processor core then accesses this specific memory area. To facilitate this, the memory address of this memory area is loaded from a reserved memory region, combined with register information from a register save area, and placed into a general-purpose register. The processor core then uses this register to access its designated memory region.
4. The system according to claim 3 , wherein the circuitry is further configured to: store the address information of the memory area in a second register; and control the processor core assigned to the thread to acquire the address information of the memory area from the second register.
This system enhancement builds upon the previous multi-core thread management system by further configuring the circuitry to store the memory area address in a dedicated register. The processor core obtains the memory area address from this second, dedicated register. This allows for quicker and more direct access to the memory location assigned to the thread.
5. The system according to claim 3 , wherein the system further comprises the plurality of processor cores, and the circuitry is configured to assign a plurality of threads to the plurality of processor cores.
Extending the previously described multi-core thread management system, this system includes multiple processor cores. The management circuitry is configured to assign multiple threads to these multiple processor cores, effectively distributing the workload across the available processing units.
6. A non-transitory computer-readable medium storing therein a program that causes a computer to execute a process, the process comprising: assigning a processor core among a plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identifying address information of a memory area, with which the processor core assigned to the thread accesses, based on identification information identifying the processor core assigned to the thread and association information stored in a memory, the association information associating identification information of the plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing a corresponding process of a corresponding thread; controlling the processor core assigned to the thread to access the memory area using the identified address information; deploying the address information of the memory area from a reserved register management area of the memory, in combination with register information of a first register from a register save area of the memory, to the first register; and controlling the processor core assigned to the thread to access the memory area by using the address information of the memory area stored in the first register.
A computer-readable medium stores instructions that, when executed, manage threads on a multi-core processor. The process involves assigning a processor core to a new thread when the process for that thread starts. The system identifies the memory area the assigned core should use by looking up the core's ID in a memory-resident table that links core IDs to specific memory regions. The assigned processor core then accesses this specific memory area. To facilitate this, the memory address of this memory area is loaded from a reserved memory region, combined with register information from a register save area, and placed into a general-purpose register. The processor core then uses this register to access its designated memory region.
7. The non-transitory computer-readable medium according to claim 6 , wherein the process further comprises: storing the address information of the memory area in a second register; and controlling the processor core assigned to the thread to acquire the address information of the memory area from the second register.
The computer-readable medium from the previous thread management description contains instructions that further enhance the process by storing the memory area address in a dedicated register. The processor core obtains the memory area address from this second, dedicated register. This allows for quicker and more direct access to the memory location assigned to the thread.
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August 11, 2015
July 11, 2017
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