One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor. Each filtering logic unit is operative to monitor the continuous processor trace information for occurrence of a predetermined condition, and to store some of the processor trace information to memory in response to occurrence of that condition.
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1. An integrated circuit comprising: a plurality of processors; a plurality of processor trace collection logic units, each processor trace collection logic unit corresponding and operatively coupled to one of the processors; and a plurality of filtering logic unit corresponding to a number of simultaneous traces supported in the integrated circuit, wherein: at least one filtering logic unit is operatively coupled to more than one of the plurality of processor trace collection logic units; and each of the plurality of filtering logic unit is configured to turn on or off storing a processor trace information collected by one of the operatively coupled collection logic unit(s).
An integrated circuit includes multiple processors, each with its own processor trace collection unit attached. These collection units are also connected to multiple filtering logic units. The number of filtering logic units matches the number of simultaneous traces the circuit can handle. Importantly, at least one filtering unit is connected to *more than one* processor trace collection unit. Each filtering unit can turn on or off the storage of trace data coming from any of its connected collection units, allowing for selective trace recording from different processors.
2. The integrated circuit of claim 1 , where each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor.
The integrated circuit, as described with multiple processors, trace collection units, and filtering logic, works by having each trace collection unit *continuously* gather processor trace information from its corresponding processor. This means the system is always monitoring the processors' activity, even before any specific events trigger data storage.
3. The integrated circuit of claim 2 , where the filtering logic unit is operative to: monitor the processor trace information for occurrence of a predetermined condition; and store some of the processor trace information to memory in response to occurrence of the predetermined condition.
In the integrated circuit where trace collection units continuously gather data, the filtering logic unit actively monitors this trace information. When a *predetermined condition* occurs (e.g., a specific function call, a memory access violation), the filtering logic stores a portion of the collected trace data to memory. This enables targeted recording of processor activity related to specific events.
4. The integrated circuit of claim 2 , where the filtering logic unit is operative to: receive a program counter value updates from at least one processor trace collection logic unit; and update a local program counter copy based on the program counter value updates and a known instruction size.
In the continuously tracing integrated circuit, the filtering logic receives program counter (PC) updates from at least one trace collection unit. The filtering logic uses these updates, along with the known size of instructions, to maintain a local, updated copy of the program counter. This allows the filter to track the execution flow of the monitored processors.
5. The integrated circuit of claim 4 , where the filtering logic unit is further operative to: receive the program counter value updates including an indication of a number of sequentially executed instructions; and update the local program counter copy based on the number of sequentially executed instructions and the known instruction size.
Building upon the program counter update mechanism, in the continuously tracing integrated circuit, the program counter updates received by the filtering logic also include information about the *number of sequentially executed instructions*. The filtering logic uses both this number and the known instruction size to update its local PC copy. This improves the accuracy of the PC tracking, especially when multiple instructions execute in a row.
6. The integrated circuit of claim 2 , where the filtering logic unit is operative to: receive a program counter value updates from at least one processor trace collection logic unit; and update a local a local program counter copy by incrementing the local program counter copy value using a program counter difference value received from the at least one processor trace collection logic unit.
In the continuously tracing integrated circuit, the filtering logic receives program counter (PC) updates from at least one trace collection unit. Instead of using a known instruction size, the filtering logic updates its local PC copy by directly *adding* a PC difference value received from the trace collection unit to the current value of the local copy. This method accounts for variable-length instructions or other factors that might cause PC increments to vary.
7. The integrated circuit of claim 4 , where the filtering logic unit is operative to: receive the program counter value updates as compressed data that is compressed by the at least one processor trace collection logic unit; and decompress the compressed data prior to updating the local program counter copy.
In the PC-tracking integrated circuit, program counter updates are sent from the trace collection unit to the filtering logic as *compressed data*. The filtering logic decompresses this data before updating its local PC copy. This reduces the bandwidth required for transferring PC updates, saving power and improving overall efficiency.
8. The integrated circuit of claim 2 , further comprising: non-transitory memory, operatively coupled to the filtering logic unit; and where the filtering logic unit is operative to store processor trace collection information to the memory in response to detecting occurrence of a predetermined condition in the processor trace information.
The integrated circuit, which continuously traces data and uses filtering logic, also includes *non-transitory memory* connected to the filtering logic. The filtering logic stores processor trace information to this memory *when a predetermined condition is detected* within the trace data. This provides a dedicated storage space for captured trace information, enabling later analysis and debugging.
9. An integrated circuit comprising: a plurality of processors; a plurality of processor trace collection logic units, each processor trace collection logic unit corresponding and operatively coupled to one of the processors; and a plurality of filtering logic units, each filtering logic unit operatively coupled to at least two processor trace collection logic units, the number of filtering logic units corresponding to a number of simultaneous traces supported in the integrated circuit.
An integrated circuit consists of multiple processors, each linked to a dedicated processor trace collection unit. These trace units are further connected to a set of filtering logic units. Each filtering logic unit connects to at least two trace collection units. The total number of filtering units corresponds to the number of simultaneous traces the integrated circuit can support. This architecture facilitates parallel tracing and filtering of processor activities.
10. The integrated circuit of claim 9 , where each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor.
The integrated circuit, with its processors, dedicated trace collection units, and filtering units, is designed to have each trace collection unit *continuously* gather processor trace data from its corresponding processor. This constant monitoring ensures no instruction or event is missed for potential analysis.
11. The integrated circuit of claim 10 , where the plurality of processors comprises forty-eight processors and the plurality of filtering logic units comprises eight filtering logic units, further where each filtering logic unit is operatively coupled to six processors.
The integrated circuit comprises forty-eight processors and eight filtering logic units, where each filtering logic unit is operatively coupled to six processors. The configuration represents a specific example of the architecture described previously, where the continuous tracing and filtering functionality is implemented with a fixed number of components.
12. A method of operating an integrated circuit comprising: collecting processor trace information continuously from a plurality of processors by a corresponding plurality of processor trace collection logic units where each processor trace collection logic unit is dedicated to one processor of the plurality of processors; broadcasting, by each of a plurality of processor trace collection logic units, processor trace information to a plurality of filtering logic units, the number of filtering logic units being less than the number of processor trace collection logic units; and storing some of the trace information to memory by at least one of the filtering logic units in response to occurrence of a predetermined condition detected by the at least one filtering logic unit.
A method for operating an integrated circuit involves continuously collecting processor trace information from multiple processors using dedicated trace collection logic units (one unit per processor). The trace collection units then broadcast this information to multiple filtering logic units, where the number of filtering units is fewer than the number of trace collection units. At least one filtering logic unit stores some of the trace information to memory when it detects a predetermined condition.
13. The method of claim 12 , further comprising: receiving, by each filtering logic unit, a program counter value updates from at least one processor trace collection logic unit; and updating, by each filtering logic unit, a local copy of the program counter value based on a known instruction size.
In the method of tracing data using continuous collection, broadcasting, and condition-based storage, each filtering logic unit also receives program counter (PC) value updates from at least one trace collection unit. Each filtering logic unit then updates its own local copy of the program counter based on a known instruction size. This enables each filter to track the execution flow of the monitored processors.
14. The method of claim 13 , further comprising: receiving, by each filtering logic unit, the program counter value updates including an indication of a number of sequentially executed instructions; and updating, by each filtering logic unit, the local copy of the program counter value based on the number of sequentially executed instructions and the known instruction size.
In the method of tracing with continuous collection, broadcasting, condition-based storage, and PC tracking, the program counter updates received by each filtering logic unit also include an indication of the *number of sequentially executed instructions*. The filtering logic uses this information, along with the known instruction size, to update its local copy of the program counter. This allows for an accurate PC reading when there are multiple instructions executed in a row.
15. The method of claim 12 , further comprising: receiving, by each filtering logic unit, a program counter value updates from at least one processor trace collection logic unit; and updating, by each filtering logic unit, a local copy of the program counter value by incrementing the local copy program value using a program counter difference value received from the at least one processor trace collection logic unit.
In the method of tracing with continuous collection, broadcasting, condition-based storage, each filtering logic unit receives program counter (PC) value updates from at least one processor trace collection logic unit. Each filtering logic unit updates its local copy of the program counter by *incrementing* the local copy's value using a program counter difference value received from the trace collection unit. This allows for more flexible PC values in case of variable instruction sizes.
16. The method of claim 13 , further comprising: receiving, by each filtering logic unit, the program counter value updates as compressed data that is compressed by the at least one processor trace collection logic unit; and decompressing, by each filtering logic unit, the compressed data prior to updating the local copy of the program counter value.
In the method of tracing with continuous collection, broadcasting, condition-based storage, and PC tracking, the program counter updates are received by each filtering logic unit as *compressed data*. The filtering logic unit must *decompress* this data before it can update its local copy of the program counter.
17. The method of claim 13 , further comprising: storing, by each filtering logic unit, processor trace collection information to memory in response to detecting occurrence of a predetermined condition in the processor trace information.
Building upon the method of tracing using continuous collection, broadcasting, condition-based storage, and program counter tracking, each filtering logic unit stores processor trace information to memory when it detects a *predetermined condition* within the trace data. This stores relevant data to memory for later access.
18. A non-volatile, non-transitory computer readable storage medium comprising: executable instructions that when executed by at least one processor of an integrated circuit fabrication system cause the integrated circuit fabrication system to: provide an individual trace collection logic unit for each processor of a plurality of processors; and provide a plurality of filtering and formatting logic units, each filtering logic unit operatively coupled to at least two trace collection logic units, the number of filtering logic units corresponding to a number of simultaneous traces supported in the integrated circuit.
A non-volatile, computer-readable storage medium holds instructions that, when executed by an integrated circuit fabrication system, cause the system to create an integrated circuit. The fabricated circuit includes an individual trace collection logic unit for *each* processor in a set of processors. It also includes multiple filtering logic units, where each filtering unit is connected to at least two trace collection units. The number of filtering units corresponds to the number of simultaneous traces supported.
19. The non-volatile, non-transitory computer readable storage medium of claim 18 , wherein the executable instructions, when executed by at least one processor of the integrated circuit fabrication system, further cause the integrated circuit fabrication system to: provide a memory unit, operatively coupled to each of the filtering and formatting logic units.
The non-volatile storage medium that builds an integrated circuit with dedicated trace and filtering units also includes instructions to create a *memory unit* that is connected to each of the filtering logic units. This memory provides a storage area for the captured trace data.
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November 14, 2014
July 11, 2017
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