A semiconductor storage device including plural bit lines, plural select gate lines that intersect with the plural bit lines, and plural memory cells that each include a p-channel memory transistor. The semiconductor storage device includes plural p-channel charging transistors that are respectively connected to the plural bit lines, and a charging line that is connected to each of the plurality of charging transistors. A controller that ON/OFF controls the charging transistors places each of the charging transistors in an ON state prior to read current flowing in a read target bit line, and that places the charging transistor connected to the read target bit line in an OFF state when read current flows in the read target bit line.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor storage device, comprising: a plurality of bit lines; a plurality of select gate lines that intersect with the plurality of bit lines; a plurality of memory cells that each include a p-channel memory transistor, with the plurality of memory cells each disposed so as to correspond to respective portions of intersection between the plurality of bit lines and the plurality of select gate lines; a source line that is connected to each of the memory transistors, and that is applied with a first specific potential when reading data stored in the memory cells; a plurality of p-channel charging transistors that are respectively connected to the plurality of bit lines; a charging line that is connected to each of the plurality of charging transistors, and that is applied with a second specific potential when reading data stored in the memory cells; and a controller that places each of the charging transistors in an ON state prior to current, corresponding to data stored in a read target memory cell of the plurality of memory cells on which data reading is to be performed, flowing in a read target bit line that is one of the plurality of bit lines and that corresponds to the read target memory cell, the controller placing a charging transistor connected to the read target bit line in an OFF state when a current corresponding to data stored in the read target memory cell flows in the read target bit line.
A semiconductor memory device uses p-channel memory transistors and includes bit lines, select gate lines, and memory cells arranged at their intersections. A source line provides a specific voltage during read operations. P-channel charging transistors are connected to each bit line, controlled by a charging line. Before reading data from a target memory cell, the controller turns ON all charging transistors to pre-charge the bit lines. During the read, the charging transistor for the target bit line is turned OFF, allowing current flow related to the stored data in the target memory cell to be sensed.
2. The semiconductor storage device of claim 1 , wherein the source line and the charging line are maintained at the same potential during a period of reading data stored in the memory cells.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, the voltage on the source line and the charging line remain the same during the data read operation.
3. The semiconductor storage device of claim 1 , wherein, during a period of reading data stored in the memory cells, each of the plurality of bit lines is in a state of being applied with a potential of the charging line, or in a state disconnected from the charging line, according to ON/OFF switching of the charging transistor.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, each bit line is either connected to the charging line's voltage (due to the charging transistor being ON) or disconnected from it (due to the charging transistor being OFF) during the read operation.
4. The semiconductor storage device of claim 1 , wherein the controller places charging transistors, among the plurality of p-channel charging transistors, that are connected to bit lines adjacent to the read target bit line, in an ON state when current corresponding to data stored in the read target memory cell flows in the read target bit line.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, the controller maintains the charging transistors connected to the bit lines adjacent to the target bit line in the ON state while reading data from the target memory cell. This helps stabilize the voltage of the neighboring bit lines.
5. The semiconductor storage device of claim 1 , wherein respective gates of the charging transistors connected to mutually adjacent bit lines among the plurality of bit lines, are each connected to the controller through mutually different control lines.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, each charging transistor connected to neighboring bit lines has a separate control line connected to the controller. This allows independent control of each charging transistor.
6. The semiconductor storage device of claim 1 , wherein a third specific potential is applied to a select gate line, that is one of the plurality of select gate lines and that corresponds to the read target memory cell, at a timing when each of the charging transistors is in an ON state, and the read target memory cell is selected.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, when all the charging transistors are turned ON to pre-charge the bit lines, a specific voltage is applied to the select gate line corresponding to the target memory cell to select that cell for reading.
7. The semiconductor storage device of claim 1 , wherein each of the plurality of bit lines is at the same potential at a timing when the read target memory cell is selected.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, all bit lines are at the same voltage level at the moment the target memory cell is selected for reading.
8. The semiconductor storage device of claim 1 , further comprising an output section that is connected to each of the plurality of bit lines, and that outputs an output voltage corresponding to a size of the current corresponding to data stored in the read target memory cell.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, an output section is connected to each bit line. This output section generates a voltage that corresponds to the amount of current flowing in the target bit line, which represents the data stored in the target memory cell.
9. The semiconductor storage device of claim 8 , wherein the current corresponding to data stored in the read target memory cell flows toward a lower potential line having a lower potential than the potential of the charging line and the source line.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, and an output section that generates a voltage corresponding to the current flowing in the bit line, the current from the target memory cell flows towards a lower voltage line. This line has a lower potential than both the charging line and source line potentials.
10. The semiconductor storage device of claim 8 , wherein the output section outputs, as the output voltage, a result of a comparison of the size of the current corresponding to data stored in the read target memory cell with a size of a reference current.
In the semiconductor memory device that includes bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, and an output section that generates a voltage corresponding to the current flowing in the bit line, the output section compares the current from the target memory cell with a reference current. The result of this comparison is output as the output voltage.
11. The semiconductor storage device of claim 1 , further comprising a global bit line connected to each of the plurality of bit lines.
The semiconductor memory device has bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read. Additionally, a global bit line is connected to each of the individual bit lines.
12. The semiconductor storage device of claim 11 , further comprising a plurality of sector select transistors provided between each of the plurality of bit lines and the global bit line.
The semiconductor memory device has bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read, and a global bit line connected to each of the individual bit lines. Sector select transistors are placed between each bit line and the global bit line, enabling the selection of sectors within the memory.
13. The semiconductor storage device of claim 1 , wherein each of the plurality of memory cells includes a select transistor connected to a corresponding bit line and a corresponding select gate line, and includes the memory transistor connected to the select transistor.
The semiconductor memory device has bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read. Each memory cell contains a select transistor, which is connected to both a bit line and a select gate line, and the memory transistor is connected to this select transistor.
14. The semiconductor storage device of claim 1 , wherein the memory transistor has a floating gate structure.
The semiconductor memory device has bit lines, select gate lines, p-channel memory transistors, a source line applying a specific voltage, p-channel charging transistors connected to each bit line, a charging line, and a controller that turns ON all charging transistors to pre-charge the bit lines before a read and turns OFF the target bit line's transistor during the read. The memory transistor within each memory cell uses a floating gate structure to store data.
15. A method of reading data stored in a memory cell of a semiconductor storage device that includes a plurality of bit lines, a plurality of select gate lines that intersect with the plurality of bit lines, a plurality of memory cells that each include a p-channel memory transistor, with the plurality of memory cells each disposed so as to correspond to respective portions of intersection between the plurality of bit lines and the plurality of select gate lines, and a source line that is connected to each of the memory transistors, the reading method comprising: connecting each of the bit lines to a charging line having a specific potential prior to current, corresponding to data stored in a read target memory cell of the plurality of memory cells on which data reading is to be performed, flowing in a read target bit line that is one of the plurality of bit lines and that corresponds to the read target memory cell; disconnecting the read target bit line from the charging line when the current corresponding to data stored in the read target memory cell flows in the read target bit line; and having the current corresponding to data stored in the read target memory cell flow toward a lower potential line having a lower potential than the potential of the charging line and the source line.
A method for reading data in a semiconductor memory device that has bit lines, select gate lines, p-channel memory transistors, and a source line, involves first connecting all bit lines to a charging line at a specific voltage. Then, when reading data from a target memory cell, the target bit line is disconnected from the charging line. After disconnection, current related to the stored data flows from the target memory cell toward a lower voltage line, which has a lower potential than both the charging line and source line potentials.
16. The reading method of claim 15 , wherein a potential at the same potential as the source lines is applied to each of the bit lines prior to the current corresponding to data stored in the read target memory cell flowing in the read target bit line.
In the method for reading data in a semiconductor memory device that has bit lines, select gate lines, p-channel memory transistors, and a source line, where all bit lines are first connected to a charging line, and the target bit line is disconnected during the read allowing current to flow to a lower potential line, the voltage applied to each bit line before reading the target memory cell is the same as the source line's voltage.
17. The reading method of claim 16 , wherein the specific potential is applied to bit lines adjacent to the read target bit line when the current corresponding to data stored in the read target memory cell flows in the read target bit line.
In the method for reading data in a semiconductor memory device that has bit lines, select gate lines, p-channel memory transistors, and a source line, where all bit lines are first connected to a charging line, and the target bit line is disconnected during the read allowing current to flow to a lower potential line, and the voltage applied to each bit line before reading the target memory cell is the same as the source line's voltage, the specific potential from the charging line is maintained on the bit lines adjacent to the target bit line during the read operation.
18. The reading method of claim 15 , wherein, at a timing when the specific potential is applied to each of the bit lines, a specific potential is applied to a select gate line, among the plurality of select gate lines, that corresponds to the read target memory cell, and the read target memory cell is selected.
In the method for reading data in a semiconductor memory device that has bit lines, select gate lines, p-channel memory transistors, and a source line, where all bit lines are first connected to a charging line, and the target bit line is disconnected during the read allowing current to flow to a lower potential line, a specific voltage is applied to the select gate line connected to the target memory cell at the same time the bit lines are pre-charged to select the target memory cell for reading.
19. The reading method of claim 15 , wherein each of the plurality of bit lines is at the same potential as each other at the timing when the read target memory cell is selected.
In the method for reading data in a semiconductor memory device that has bit lines, select gate lines, p-channel memory transistors, and a source line, where all bit lines are first connected to a charging line, and the target bit line is disconnected during the read allowing current to flow to a lower potential line, all bit lines are at the same voltage when the target memory cell is selected for reading.
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July 27, 2016
July 11, 2017
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