An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread.
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1. A hardware processor comprising: a decoder to decode an instruction into a decoded instruction; and an execution unit to execute the decoded instruction to: generate a wake indication for a second thread that is to be spawned from a first thread to cause a power control circuit to transition a processing element that is to execute the second thread from a first power state to a second power state within an amount of time to transition the processing element from the first power state to the second power state before the spawn, wherein the first power state and the second power state are lower power consumption states than an active power state.
A hardware processor prepares a core for a new thread by waking it up early. When a first thread wants to spawn a second thread, the processor decodes an instruction to generate a "wake indication". This signal tells the power control circuit to transition the core, which will run the second thread, from a low-power state (first power state) to a less-low-power state (second power state). This transition happens *before* the second thread actually starts. Both power states are lower than the active, fully powered state, but waking up to the second power state ahead of time reduces latency.
2. The hardware processor of claim 1 , wherein the execution unit is to execute the decoded instruction to store the wake indication in a control register.
The hardware processor described above stores the "wake indication" for the second thread in a specific control register within the processor. This register acts as a flag or signal that the power control circuit monitors, triggering the transition from the first low-power state to the second, less-low-power state, in preparation for the second thread to begin execution.
3. The hardware processor of claim 1 , wherein the wake indication includes a processing element identifier to identify the processing element from a plurality of processing elements.
In the hardware processor described where the first thread wakes a second thread early, the generated "wake indication" includes a processing element identifier. This identifier is used in systems with multiple cores to specify *which* core should be woken up. This allows a main core to signal a specific helper core to prepare for a new thread, ensuring the correct core transitions to a ready state.
4. The hardware processor of claim 1 , wherein the first thread is a main thread and the second thread is a helper thread to return data from the second thread to the first thread.
The hardware processor described uses the early wake-up mechanism specifically when a "main" thread spawns a "helper" thread. The main thread delegates a task to the helper thread and expects data to be returned. The early wake-up scheme minimizes the delay in the helper thread's execution, allowing it to quickly process the data and return the result to the main thread, improving overall application performance.
5. The hardware processor of claim 1 , wherein the first thread is to be executed on a first core and the processing element is a second core.
The hardware processor described uses the early wake-up mechanism when the first thread (the thread initiating the new thread) runs on a first core, and the second thread (the new thread being spawned) is intended to run on a *different* core. The core which runs the second thread is the processing element which transitions from the first low-power state to the second, less-low-power state.
6. The hardware processor of claim 5 , wherein the first core includes the decoder and the execution unit.
In the multi-core hardware processor described above where the first thread runs on a first core and the second thread is to run on another core, the first core (the one running the thread that initiates the second thread), contains the decoder and execution unit that are responsible for generating the wake-up signal for the other core. This means the instruction to spawn the helper thread, and the logic to wake the target core, resides within the core initiating the new thread.
7. The hardware processor of claim 1 , wherein the first power state is a first Advanced Configuration and Power Interface (ACPI) non-operating power state, the second power state is a second ACPI non-operating power state, and the active power state is an ACPI operating state.
The hardware processor's power states in the early wake scheme are defined using the ACPI (Advanced Configuration and Power Interface) standard. The first power state, the deepest sleep, is an ACPI non-operating state. The second power state, a less deep sleep used for early wake, is another ACPI non-operating state, but higher than the first. The active power state, where the core is fully running, is the ACPI operating state. The processor transitions from one non-operating state to another, prior to full activation.
8. A method comprising: decoding an instruction into a decoded instruction with a decoder of a hardware processor; and executing the decoded instruction with an execution unit of the hardware processor to: generate a wake indication for a second thread that is to be spawned from a first thread to cause a power control circuit to transition a processing element that is to execute the second thread from a first power state to a second power state within an amount of time to transition the processing element from the first power state to the second power state before the spawn, wherein the first power state and the second power state are lower power consumption states than an active power state.
A method for a hardware processor to prepare for a new thread involves decoding an instruction into a decoded instruction using a decoder; and executing the decoded instruction with an execution unit to generate a "wake indication" for a second thread (to be spawned). This indication causes a power control circuit to transition the target core from a low-power state to a less-low-power state *before* the new thread starts. The low-power states consume less power than the active state, but this method avoids delays by pre-emptively waking the core.
9. The method of claim 8 , wherein the executing comprises storing the wake indication in a control register.
The method for preparing for a new thread as described includes storing the generated "wake indication" in a designated control register. The power control circuit monitors this register, and upon detecting the wake indication, initiates the process of transitioning the target core from the first low-power state to the second, less-low-power state.
10. The method of claim 8 , wherein the wake indication includes a processing element identifier to identify the processing element from a plurality of processing elements.
In the method for preparing a core for a new thread, the "wake indication" includes a specific processing element identifier. This identifier specifies *which* processing element (core) from a group of cores should be awakened. The wake indication is targeted towards the core that is expected to execute the second thread.
11. The method of claim 8 , wherein the first thread is a main thread and the second thread is a helper thread to return data from the second thread to the first thread.
The described method of waking up a core early is used when a "main" thread is spawning a "helper" thread. The helper thread performs a specific task and returns data to the main thread. Early wake-up minimizes the delay in the helper thread's execution, enabling faster data processing and return, which improves overall performance.
12. The method of claim 8 , wherein the first thread executes on a first core of the hardware processor and the processing element is a second core of the hardware processor.
In the described method, the first thread (initiating thread) runs on a first core, while the core that will execute the second thread is a *different* core. The method prepares the *second* core for the new thread. The method is employed in a multi-core system, where threads can be assigned to and executed on separate cores.
13. The method of claim 12 , wherein the first core includes the decoder and the execution unit.
In the multi-core method where the first thread and the second thread will run on different cores, the first core contains the decoder and execution unit that create the wake signal. The core spawning the thread also handles waking up the target core for the new thread.
14. The method of claim 8 , wherein the first power state is a first Advanced Configuration and Power Interface (ACPI) non-operating power state, the second power state is a second ACPI non-operating power state, and the active power state is an ACPI operating state.
In the described method, power states are based on the ACPI standard. The "first power state" is an ACPI non-operating power state, and the "second power state" is also an ACPI non-operating power state, but at a higher power level than the first. The full "active power state" is an ACPI operating state.
15. A non-transitory machine readable medium including code, that when executed by a machine, causes the machine to perform a method comprising: decoding an instruction into a decoded instruction with a decoder of a hardware processor; and executing the decoded instruction with an execution unit of the hardware processor to: generate a wake indication for a second thread that is to be spawned from a first thread to cause a power control circuit to transition a processing element that is to execute the second thread from a first power state to a second power state within an amount of time to transition the processing element from the first power state to the second power state before the spawn, wherein the first power state and the second power state are lower power consumption states than an active power state.
A computer-readable medium stores instructions that, when executed, cause a processor to decode an instruction and then execute the decoded instruction to generate a wake indication for a second thread, prior to its spawning. This wake indication triggers a power control circuit to transition a target core from a low-power state to a less-low-power state, to prepare the core for the new thread's execution, reducing latency.
16. The non-transitory machine readable medium of claim 15 , wherein the executing comprises storing the wake indication in a control register.
The computer-readable medium described above, when executed, causes the processor to store the "wake indication" in a specific control register, as part of the process for waking a core early to prepare for a new thread.
17. The non-transitory machine readable medium of claim 15 , wherein the wake indication includes a processing element identifier to identify the processing element from a plurality of processing elements.
The computer-readable medium described where it causes a processor to prepare a core for a second thread, the wake indication contains an element to identify which core to wake from its plurality of cores, which should be woken up to execute the second thread.
18. The non-transitory machine readable medium of claim 15 , wherein the first thread is a main thread and the second thread is a helper thread to return data from the second thread to the first thread.
In the computer-readable medium described above, where code prepares for a second thread by issuing a wake indication, the use case is when the first thread is a "main" thread and the second thread being spawned is a "helper" thread tasked with returning data back to the main thread.
19. The non-transitory machine readable medium of claim 15 , wherein the first thread executes on a first core of the hardware processor and the processing element is a second core of the hardware processor.
The computer-readable medium described stores code that prepares a processor for a second thread on a separate core from the first. The first thread executes on a first core of the hardware processor and the processing element that is being prepared with the wake indication is a second core of the hardware processor.
20. The non-transitory machine readable medium of claim 19 , wherein the first core includes the decoder and the execution unit.
The computer-readable medium described where the method causes the spawning and preparation of a separate core for the spawned second thread, the code resides and is executed by the first core, which contains the decoder and execution unit.
21. The non-transitory machine readable medium of claim 15 , wherein the first power state is a first Advanced Configuration and Power Interface (ACPI) non-operating power state, the second power state is a second ACPI non-operating power state, and the active power state is an ACPI operating state.
In the computer-readable medium described above, the power states involved in the core early-wake system use the ACPI standard, with the first state being an ACPI non-operating power state, the second state being a separate, higher ACPI non-operating power state, and the final active state being an ACPI operating state.
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September 27, 2016
August 1, 2017
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