A method for manufacturing a fin field-effect transistor (FinFET) device, comprises patterning a first layer on a substrate to form at least one fin, patterning a second layer under the first layer to remove a portion of the second layer on sides of the at least one fin, forming a sacrificial gate electrode on the at least one fin, and a spacer on the sacrificial gate electrode, selectively removing the sacrificial gate electrode, depositing an oxide layer on top and side portions of the at least one fin corresponding to a channel region of the at least one fin, performing thermal oxidation to condense the at least one fin in the channel region until a bottom portion of the at least one fin is undercut, and stripping a resultant oxide layer from the thermal oxidation, leaving a gap in the channel region between a bottom portion of the at least one fin and the second layer.
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1. A fin field-effect transistor (FinFET) device, comprising: at least one fin formed on an oxide layer; a gap in a channel region of the at least one fin between a bottom portion of the at least one fin and the oxide layer, wherein the gap includes an undercut in the bottom portion of the at least one fin, and a recessed portion of the oxide layer; a gate structure around the at least one fin, including in the gap on an underside of the at least one fin; and a spacer layer formed on a side of the gap; wherein the gap includes a stepped portion between the undercut and the recessed portion; and wherein the stepped portion is formed in the spacer layer.
A FinFET transistor has a fin sitting on an oxide layer. A key feature is a gap carved out in the channel region of the fin. This gap isn't just a simple void; it includes an undercut in the bottom part of the fin itself, plus a recessed area in the oxide layer underneath. The gate, which controls the transistor, wraps completely around the fin, even reaching into this undercut gap. A spacer layer sits beside this gap. Notably, the gap has a stepped shape – like a mini staircase – and this step is formed within the spacer layer itself.
2. The fin field-effect transistor (FinFET) device of claim 1 , wherein the gate structure comprises a dielectric layer formed on the spacer layer and on the stepped portion.
Building on the FinFET transistor described previously, the gate structure includes a dielectric layer. This dielectric layer isn't just anywhere; it's specifically formed on the spacer layer *and* on that stepped portion of the gap described earlier. This ensures good insulation and control in that critical area.
3. The fin field-effect transistor (FinFET) device of claim 2 , wherein the gate structure further comprises a metal layer formed on the dielectric layer.
Expanding on the FinFET transistor with the dielectric layer on the spacer and stepped portion, the gate structure *also* contains a metal layer. This metal layer is placed on top of the dielectric layer. This combination of dielectric and metal improves the gate's ability to control the flow of current through the fin.
4. The fin field-effect transistor (FinFET) device of claim 2 , wherein the dielectric layer is further formed an underside of the bottom portion of the at least one fin.
Further expanding on the FinFET transistor with the dielectric layer on the spacer and stepped portion, the dielectric layer is also formed on the underside of the undercut portion of the fin. This ensures even better gate control and insulation all around the fin in that critical channel region.
5. The fin field-effect transistor (FinFET) device of claim 1 , wherein the gate structure comprises a dielectric layer formed around the at least one fin, and a metal layer formed on the dielectric layer.
The FinFET transistor features a gate structure consisting of a dielectric layer completely surrounding the fin. A metal layer is then formed on top of this dielectric layer, further enhancing the gate's control over the transistor's channel.
6. A semiconductor device, comprising: at least one fin formed on an oxide layer, wherein the at least one fin comprises silicon germanium; a gap in a channel region of the at least one fin between a bottom portion of the at least one fin and the oxide layer, wherein the gap includes an undercut in the bottom portion of the at least one fin, and a recessed portion of the oxide layer; a gate structure around the at least one fin, including in the gap on an underside of the at least one fin; and a spacer layer formed on a side of the gap; wherein the gap includes a stepped portion between the undercut and the recessed portion; and wherein the stepped portion is formed in the spacer layer.
This semiconductor device includes a fin made of silicon germanium on an oxide layer. Crucially, there's a gap in the channel region between the fin's bottom and the oxide. This gap is special: it includes an undercut in the fin's bottom and a recessed area in the oxide. The gate surrounds the fin, even within the gap's underside. A spacer is on the gap's side. The gap is stepped, and this step is formed within the spacer layer itself.
7. The semiconductor device of claim 6 , wherein the gate structure comprises a dielectric layer formed on the spacer layer and on the stepped portion.
Building upon the previous semiconductor device with the SiGe fin, the gate structure incorporates a dielectric layer formed on the spacer layer *and* on the stepped portion of the gap. This ensures good insulation and control in that critical area.
8. The semiconductor device of claim 7 , wherein the gate structure further comprises a metal layer formed on the dielectric layer.
Expanding on the previous semiconductor device with the SiGe fin and the dielectric layer on the spacer and stepped portion, the gate structure *also* contains a metal layer. This metal layer sits on top of the dielectric layer, enhancing the gate's control.
9. The semiconductor device of claim 7 , wherein the dielectric layer is further formed an underside of the bottom portion of the at least one fin.
Further expanding on the previous semiconductor device with the SiGe fin and the dielectric layer on the spacer and stepped portion, the dielectric layer extends to the underside of the undercut portion of the fin. This provides enhanced gate control and insulation around the fin's channel.
10. The semiconductor device of claim 6 , wherein the gate structure comprises a dielectric layer formed around the at least one fin, and a metal layer formed on the dielectric layer.
The semiconductor device with the SiGe fin features a gate structure consisting of a dielectric layer completely surrounding the fin. A metal layer is then formed on top of the dielectric layer, further enhancing the gate's control over the transistor's channel.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 22, 2016
August 1, 2017
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