A semiconductor device is provided, including two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device, a dielectric structure entirely filling a space between the nanowires and which is in contact with the nanowires, a gate dielectric and a gate covering a first of the nanowires, sidewalls of the nanowires and sidewalls of the dielectric structure when the nanowires are superimposed one on top of the other, or covering a part of the upper faces of the nanowires and a part of an upper face of the dielectric structure when the nanowires are arranged next to one another, and wherein the dielectric structure comprises a portion of dielectric material with a relative permittivity greater than or equal to 20.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device, comprising: at least two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device; a dielectric structure entirely filling a space extending between the at least two semiconductor nanowires and which is in contact with the at least two semiconductor nanowires; and a gate dielectric and a gate covering at least a first of the at least two semiconductor nanowires, sidewalls of the two semiconductor nanowires, and sidewalls of the dielectric structure when the at least two semiconductor nanowires are superimposed one on top of the other, or covering a part of the upper faces of the at least two semiconductor nanowires and a part of an upper face of the dielectric structure when the at least two semiconductor nanowires are arranged next to one another, wherein the dielectric structure comprises at least one portion of dielectric material with a relative permittivity greater than or equal to 20, and wherein the at least two semiconductor nanowires are arranged next to one another such that a part of the dielectric structure is arranged under the at least two semiconductor nanowires and between the at least two semiconductor nanowires.
A semiconductor device has at least two semiconductor nanowires that are either stacked on top of each other or placed next to each other, with a space between them. These nanowires form the channel regions of the device. A dielectric structure completely fills the space between the nanowires and touches them. A gate dielectric and a gate cover at least one of the nanowires. If the nanowires are stacked, the gate covers the nanowire sidewalls and the dielectric structure's sidewalls. If the nanowires are next to each other, the gate covers part of the top surfaces of the nanowires and part of the top surface of the dielectric structure. The dielectric structure includes a material with a relative permittivity (dielectric constant) of 20 or greater. The two nanowires are arranged so that a part of the dielectric structure is arranged under and between them.
2. The semiconductor device according to claim 1 , wherein the semiconductor nanowires are parallel with respect to one another.
In the semiconductor device described in the previous claim where two nanowires form the channel regions of the device, are separated by a high-permittivity dielectric, and are partially covered by a gate, the semiconductor nanowires are parallel to each other.
3. The semiconductor device according to claim 2 , wherein each semiconductor nanowire comprises, in a plane perpendicular to a direction according to which the semiconductor nanowires extend, a section of rectangular shape.
In the semiconductor device described in the previous claim where two parallel nanowires form the channel regions of the device, are separated by a high-permittivity dielectric, and are partially covered by a gate, each semiconductor nanowire has a rectangular cross-section when viewed perpendicular to its length.
4. The semiconductor device according to claim 1 , wherein each semiconductor nanowire is surrounded by a dielectric interface layer, the dielectric structure further comprising portions of the dielectric interface layers arranged between the semiconductor nanowires and in contact with the at least one portion of dielectric material.
In the semiconductor device described in the first claim where two nanowires form the channel regions of the device, are separated by a high-permittivity dielectric, and are partially covered by a gate, each semiconductor nanowire is surrounded by a dielectric interface layer. The dielectric structure also includes portions of these interface layers, positioned between the nanowires and touching the high-permittivity material.
5. The semiconductor device according to claim 1 , further comprising at least one additional semiconductor nanowire in addition to the two semiconductor nanowires, said at least one additional semiconductor nanowire and the two semiconductor nanowires being superimposed one on top of another; and at least one additional dielectric structure in addition to the dielectric structure, wherein two adjacent semiconductor nanowires are spaced one from the other by one of the dielectric structures extending between said two adjacent semiconductor nanowires and in contact with said two adjacent semiconductor nanowires, and wherein the gate dielectric and the gate also cover sidewalls of the at least one additional semiconductor nanowire and sidewalls of the at least one additional dielectric structure.
The semiconductor device described in the first claim where two nanowires form the channel regions of the device, are separated by a high-permittivity dielectric, and are partially covered by a gate, further contains one or more additional semiconductor nanowires stacked on top of the original two. It also contains additional dielectric structures. Each pair of adjacent nanowires is separated by one of these dielectric structures, which extends between and touches the nanowires. The gate dielectric and gate also cover the sidewalls of the additional nanowire(s) and the sidewalls of the additional dielectric structure(s).
6. The semiconductor device according to claim 1 , further comprising source and drain regions between which extend the semiconductor nanowires or formed by parts of semiconductor nanowires, with the dielectric structure being in contact with the source and drain regions and/or juxtaposed with the source and drain regions.
The semiconductor device described in the first claim where two nanowires form the channel regions of the device, are separated by a high-permittivity dielectric, and are partially covered by a gate, includes source and drain regions. The nanowires extend between, or are partially formed by, these source and drain regions. The dielectric structure is in contact with and/or adjacent to the source and drain regions.
7. A semiconductor device, comprising: at least two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device; a dielectric structure entirely filling a space extending between the at least two semiconductor nanowires and which is in contact with the at least two semiconductor nanowires; and a gate dielectric and a gate covering at least a first of the at least two semiconductor nanowires, sidewalls of the two semiconductor nanowires, and sidewalls of the dielectric structure when the at least two semiconductor nanowires are superimposed one on top of the other, or covering a part of the upper faces of the at least two semiconductor nanowires and a part of an upper face of the dielectric structure when the at least two semiconductor nanowires are arranged next to one another, wherein the dielectric structure comprises at least one portion of dielectric material with a relative permittivity greater than or equal to 20, and wherein each semiconductor nanowire is surrounded by a dielectric interface layer, the dielectric structure further comprising portions of the dielectric interface layers arranged between the at least two semiconductor nanowires and in contact with the at least one portion of dielectric material.
A semiconductor device has at least two semiconductor nanowires that are either stacked on top of each other or placed next to each other, with a space between them. These nanowires form the channel regions of the device. A dielectric structure completely fills the space between the nanowires and touches them. A gate dielectric and a gate cover at least one of the nanowires. If the nanowires are stacked, the gate covers the nanowire sidewalls and the dielectric structure's sidewalls. If the nanowires are next to each other, the gate covers part of the top surfaces of the nanowires and part of the top surface of the dielectric structure. The dielectric structure includes a material with a relative permittivity (dielectric constant) of 20 or greater. Each semiconductor nanowire is surrounded by a dielectric interface layer, and the dielectric structure also includes portions of these interface layers positioned between the nanowires and touching the high-permittivity material.
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December 23, 2014
August 8, 2017
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