The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.
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1. A method of forming a conductive through silicon via in a semiconductor wafer, comprising the steps: a.) providing a semiconductor wafer including: a substrate defining opposed top and bottom surfaces; a circuitry which is disposed on the top surface of the substrate and comprises a plurality of metal interconnect layers integrated therein in spaced relation to each other; a first pad which has a solid portion and a plurality of perforations, and is provided in a first one of the plurality of metal interconnect layers; and a second pad which has a solid portion and a plurality of perforations, and is provided in a second one of the plurality of metal interconnect layers in a position relative to the first pad such that the plurality of perforations of the first pad are aligned with respective sections of the solid portion defined by the plurality of perforations of the second pad; b.) etching the bottom surface of the substrate, which forms a through hole therein which exposes the first pad; and c.) forming a conductive via in the through hole, which extends into electrically conductive contact with the first pad.
A method for creating a through-silicon via (TSV) in a semiconductor wafer. The process involves starting with a wafer that has a substrate with top and bottom surfaces. Circuitry including multiple metal layers is built on the top surface. The wafer includes two pads: a first pad with solid sections and holes in one metal layer, and a second pad with solid sections and holes in another metal layer. The pads are positioned so the first pad's holes align with the second pad's solid sections. A hole is etched from the bottom of the wafer to expose the first pad, and then a conductive material is deposited in the hole to make contact with the first pad, forming the TSV.
2. The method of claim 1 wherein step (c) comprises plating a conductive metal in the through hole to form a conductive metal layer which defines a central bore and extends into electrically conductive contact with the first pad.
The method of forming a TSV involves plating a conductive metal into the etched hole to create a conductive metal layer. This metal layer has a central opening and makes electrical contact with the first pad. This plating process forms the conductive via.
3. The method of claim 2 wherein step (b) further comprises etching at least one of the inter-layer dielectrics in a manner wherein the conductive metal layer further extends through at least some of the perforations of the first pad and the etched one of the inter-layer dielectrics into electrically conductive contact with the solid portion of the second pad.
Building on the method of forming a TSV by plating conductive metal to create a via with a central bore, this process also includes further etching of the insulating layers between the metal layers. Specifically, the conductive metal that was plated in the through hole not only contacts the first pad, but also extends through some of the holes in the first pad and into the etched insulating layer. This extension allows the conductive metal to make contact with the solid portion of the second pad, improving electrical connectivity between the TSV and the metal layers.
4. The method of claim 2 wherein step (c) further comprises filling the central bore of the conductive metal layer with a conductive adhesive.
After plating the conductive metal to form the via with a central bore, the method includes filling the central opening with a conductive adhesive to further enhance the electrical and mechanical properties of the TSV. This conductive adhesive fills the void in the plated metal.
5. The method of claim 2 wherein step (c) further comprises plating the conductive metal onto a portion of the bottom surface of the substrate to form a metal plane thereon which is electrically connected to the conductive metal layer.
After plating conductive metal to form the via with a central bore, the method includes plating the conductive metal onto a portion of the wafer's bottom surface. This creates a metal plane on the bottom that is electrically connected to the conductive metal layer of the TSV. This provides a larger area for electrical connection on the bottom side of the wafer.
6. The method of claim 1 wherein step (c) comprises forming an insulting material layer in the through hole, which defines a central bore and filling the central bore with a conductive metal which extends into electrically conductive contact with the first pad.
This TSV formation method involves creating an insulating layer inside the etched hole, which itself defines a central opening. This central opening is then filled with conductive metal that makes electrical contact with the first pad. Therefore, the via consists of a conductive metal core surrounded by an insulating layer inside the TSV.
7. The method of claim 6 wherein step (b) further comprises etching at least one of the plurality of stacked inter-layer dielectrics in a manner wherein the conductive metal further extends through at least some of the plurality of perforations of the first pad and the etched one of the plurality of stacked inter-layer dielectrics into electrically conductive contact with the solid portion of the second pad.
This method involves etching insulating layers between the stacked metal interconnect layers. The conductive metal, after being deposited in the insulating-lined via, goes on to extend through some of the perforations of the first pad. As it extends through, it connects with the etched region of the insulating layers, and eventually comes into contact with the solid portion of the second pad.
8. The method of claim 6 wherein the conductive metal further extends to a portion of the bottom surface of the substrate and forms a metal plane thereon.
Building on the method where the through hole is lined with an insulating material, and then filled with conductive metal, this method also includes extending the conductive metal to a portion of the bottom surface of the substrate to form a metal plane on the bottom. This provides a larger area for electrical connection on the bottom side of the wafer.
9. A method of forming a conductive through silicon via in a semiconductor wafer, comprising the steps: a.) providing a semiconductor wafer including: a substrate defining opposed top and bottom surfaces; a circuitry which is disposed on the top surface of the substrate and comprises a plurality of metal interconnect layers; a first pad which has a solid portion and a plurality of perforations, and is provided in a first one of the plurality of metal interconnect layers; and a second pad which has a solid portion and a plurality of perforations, and is provided in a second one of the plurality of metal interconnect layers in a position relative to the first pad such that the plurality of perforations of the first pad are aligned with respective sections of the solid portion defined by the plurality of perforations of the second pad; b.) etching the bottom surface of the substrate, which forms a first through hole therein which exposes the first pad; and c.) filling a conductive material into the first through hole, which extends into electrically conductive contact with the first pad.
A method for creating a through-silicon via (TSV) in a semiconductor wafer. The process involves starting with a wafer that has a substrate with top and bottom surfaces. Circuitry including multiple metal layers is built on the top surface. The wafer includes two pads: a first pad with solid sections and holes in one metal layer, and a second pad with solid sections and holes in another metal layer. The pads are positioned so the first pad's holes align with the second pad's solid sections. A hole is etched from the bottom of the wafer to expose the first pad, and then a conductive material is filled into the hole to make contact with the first pad, forming the TSV.
10. The method of claim 9 , wherein step (c) comprises plating a conductive metal in the first through hole.
The TSV formation process includes plating a conductive metal into the etched hole. This metal makes electrical contact with the first pad.
11. The method of claim 10 , wherein the conductive metal further extends to a portion of the bottom surface of the substrate and forms a metal plane thereon.
Building on the method of forming a TSV by plating conductive metal to create a via, this method also includes extending the conductive metal to a portion of the wafer's bottom surface. This creates a metal plane on the bottom that is electrically connected to the conductive metal layer of the TSV. This provides a larger area for electrical connection on the bottom side of the wafer.
12. A method of forming a conductive through silicon via in a semiconductor wafer, comprising the steps: a.) providing a semiconductor wafer including: a substrate defining opposed top and bottom surfaces; active circuitry which is disposed on the top surface of the substrate and comprises a plurality of stacked inter-layer dielectrics having a plurality of metal interconnect layers integrated therein in spaced relation to each other; a first pad which has a solid portion and a plurality of perforations, and is provided in a first one of the plurality of metal interconnect layers; and a second pad which has a solid portion and a plurality of perforations, and is provided in a second one of the plurality of metal interconnect layers in a position relative to the first pad such that the plurality of perforations of the first pad are aligned with respective sections of the solid portion defined by the plurality of perforations solid portion of the second pad; b.) etching the bottom surface of the substrate, which forms a first through hole therein which exposes the first pad; c.) etching at least some of the plurality of stacked inter-layer dielectrics exposed by the plurality of perforations of the first pad, which forms a second through hole therein which exposes the solid portion of the second pad; d.) disposing an insulating layer on the side wall of the first through hole, which defines a central bore; and e.) filling a conductive material into the central bore, which extends into electrically conductive contact with the first pad.
A method for creating a through-silicon via (TSV) in a semiconductor wafer. The process involves starting with a wafer that has a substrate with top and bottom surfaces. Active circuitry with multiple stacked insulating layers and metal interconnects is built on the top surface. The wafer includes two pads: a first pad with solid sections and holes in one metal layer, and a second pad with solid sections and holes in another metal layer. The pads are positioned so the first pad's holes align with the second pad's solid sections. A first hole is etched from the bottom to expose the first pad. Then, the insulating layers exposed by the holes in the first pad are etched to create a second hole exposing the second pad's solid sections. An insulating layer is deposited on the sidewall of the first hole, creating a bore. Finally, a conductive material is filled into this bore, making electrical contact with the first pad.
13. The method of claim 12 , wherein step (e) comprises plating a conductive metal in the central bore.
This method involves forming the TSV's via by plating a conductive metal inside the central bore.
14. The method of claim 13 , wherein the conductive metal further extends to a portion of the bottom surface of the substrate and forms a metal plane thereon.
Building on the method of plating conductive metal to form a TSV in a central bore, the method extends the conductive metal to a portion of the wafer's bottom surface, forming a metal plane there.
15. The method of claim 13 , wherein the conductive metal is plated in a manner that the conductive metal further extends and contacts the solid portion of the second pad.
After creating a central bore lined with an insulating material, the via is created by plating a conductive metal inside the central bore. The conductive metal plated also extends and contacts the solid portion of the second pad.
16. The method of claim 15 , wherein the conductive metal further extends to a portion of the bottom surface of the substrate and forms a metal plane thereon.
After plating conductive metal inside the TSV's central bore, connecting to the solid portion of the second pad, the method further includes extending the conductive metal to a portion of the wafer's bottom surface, forming a metal plane there.
17. The method of claim 13 , wherein the conductive metal is plated in a manner that it further extends into the first through hole and contacts the solid portion of the second pad.
After plating conductive metal inside the TSV's central bore, the conductive metal also extends into the first hole and contacts the solid portion of the second pad.
18. The method of claim 13 , wherein the conductive metal is plated in a manner that it further extends to a portion of the bottom surface of the substrate and forms a metal plane thereon.
After plating conductive metal inside the TSV's central bore, the conductive metal extends to a portion of the bottom surface of the substrate and forms a metal plane there.
19. The method of claim 9 , wherein step (c) comprises disposing an insulating layer on the side wall of the first through hole so that the insulating layer defines a central bore, and thereafter filling the conductive material into the central bore.
This method forms a TSV in a semiconductor wafer by first creating a hole that exposes a first pad, and then lining the hole with an insulating material to define a central opening or bore. This is followed by filling the central bore with a conductive material to create the via.
20. The method of claim 19 , wherein step (c) comprises plating a conductive metal in the central bore.
After lining the TSV's through hole with an insulating material, defining a central bore, the conductive material filling the bore is a plated conductive metal.
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August 21, 2014
August 8, 2017
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