Systems and methods for transforming a Central Processing Unit (CPU) socket into a memory and/or Input/Output (I/O) expander. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of CPU sockets, each of the CPU sockets having one or more cores, and each of the one or more cores being associated with a respective one or more electronic circuits, the one or more electronic circuits including at least one of: a memory controller or an input/output (I/O) controller; and a Basic Input/Output System (BIOS) circuit coupled to the plurality of CPU sockets, the BIOS circuit having access to program instructions that, upon execution by the BIOS, cause the IHS to: initialize the plurality of CPU sockets; and report an electronic circuit associated to a first core of a first CPU socket as being instead associated with a second core of a second CPU socket.
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1. An Information Handling System (IHS), comprising: a plurality of Central Processing Unit (CPU) circuits, wherein each of the CPU circuits comprises a core and at least one of: a memory controller or an input/output (I/O) lane; and a Basic Input/Output System (BIOS) coupled to the plurality of CPU circuits, the BIOS having program instructions stored thereon that, upon execution by the IHS, cause the IHS to: identify a memory controller or I/O lane of a first CPU circuit as belonging to a second CPU circuit; identify the first CPU circuit as not having any cores; and create or modify an Advanced Configuration and Power Interface (ACPI) System Locality Information Table (SLIT) to identify a memory controller of the first CPU circuit as being a remote memory coupled to the second CPU circuit.
This invention relates to an information handling system (IHS) with multiple central processing unit (CPU) circuits, each containing a core and at least one memory controller or input/output (I/O) lane. The system includes a Basic Input/Output System (BIOS) that executes instructions to manage CPU configurations. The BIOS identifies a memory controller or I/O lane from a first CPU circuit and assigns it to a second CPU circuit. It also determines that the first CPU circuit lacks any cores. The BIOS then creates or modifies an Advanced Configuration and Power Interface (ACPI) System Locality Information Table (SLIT) to classify the memory controller of the first CPU circuit as a remote memory resource linked to the second CPU circuit. This approach optimizes system resource allocation by dynamically reassigning hardware components between CPU circuits, improving efficiency in multi-processor systems. The solution addresses challenges in managing memory and I/O resources in complex computing environments, particularly where CPU circuits may lack cores but still contribute valuable hardware components. The ACPI SLIT modification ensures proper system awareness of memory locality, enhancing performance and resource utilization.
2. The IHS of claim 1 , wherein the plurality of CPU circuits include a single multi-core processor.
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, uses a single multi-core processor instead of multiple separate CPU chips. This means that all the cores, memory controllers, and I/O lanes being remapped reside within the same physical processor package. The BIOS still performs the same reassignment and table modifications, but the components are physically closer together within the same processor.
3. The IHS of claim 1 , wherein each core in each of the plurality of CPU circuits is configured to operate as a logical processor.
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, has each core in each CPU configured to operate as a logical processor. Each core is presented to the operating system as an independent processing unit, allowing the OS to schedule tasks across all cores regardless of the memory or I/O remapping performed by the BIOS.
4. The IHS of claim 1 , wherein the memory controller or I/O lane is physically disposed closer to a first core of the first CPU circuit than to a second core of the second CPU circuit.
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, has the memory controller or I/O lane physically located closer to a first core of the first CPU, despite being logically assigned to a second core of the second CPU. This means the physical wiring and placement of the memory controller or I/O lane are nearer the original CPU core before the BIOS remapping.
5. The IHS of claim 1 , wherein the identifying enables a memory controller of the second CPU circuit to communicate with two or more dual in-line memory modules (DIMMs).
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, allows a memory controller assigned to the second CPU to connect to two or more DIMM memory modules. This enables increased memory capacity and bandwidth for the second CPU by utilizing the remapped memory controller from the first CPU.
6. The IHS of claim 1 , wherein the program instructions, upon execution by the IHS, further cause the IHS to create or modify a Local Advanced Programmable Interrupt Controller (LAPIC) table of an Advanced Configuration and Power Interface (ACPI).
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, after remapping the controllers, further modifies the ACPI LAPIC table. This table manages interrupt routing.
7. The IHS of claim 1 , wherein the program instructions, upon execution by the IHS, further cause the IHS to modify an Advanced Configuration and Power Interface (ACPI) Static Resource Affinity Table (SRAT) to identify a memory controller of the first CPU circuit as being coupled directly to a core of the second CPU circuit.
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, further modifies the ACPI SRAT table after the remapping. The SRAT table is updated to show that the memory controller from the first CPU is now directly connected to a core of the second CPU. This ensures the OS understands the memory topology after the reassignment.
8. The IHS of claim 1 , wherein the program instructions, upon execution by the IHS, further cause the IHS to create or modify Advanced Configuration and Power Interface (ACPI) proximity (PXM) information to report one or more Peripheral Component Interconnect Express (PCIe) root ports of the first CPU circuit as logical PCIe root ports belonging to the second CPU circuit.
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, further configures ACPI proximity information to remap PCIe root ports. The system reports PCIe root ports of the first CPU as belonging to the second CPU. This allows I/O devices connected to the first CPU's PCIe ports to be logically managed by the second CPU.
9. The IHS of claim 1 , wherein the program instructions, upon execution by the IHS, further cause the IHS to, in response to a System Management Mode (SMM) of operation being invoked to address a memory or I/O error of the first CPU circuit during Operating System (OS) runtime, report the error as having been originated by the second CPU circuit.
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, is designed to handle errors transparently. If a memory or I/O error occurs in the remapped resources of the first CPU during OS runtime, and the system enters System Management Mode (SMM) to handle the error, the system will report the error as originating from the second CPU. This hides the remapping and simplifies error handling.
10. The IHS of claim 1 , wherein the identifying operations occur before the IHS boots into an Operating System (OS).
The Information Handling System described where the BIOS reassigns memory controllers or I/O lanes from one CPU to another, performs the identifying and remapping operations before the OS boots. This ensures that the operating system sees the modified memory and I/O configuration from the start, avoiding potential conflicts or errors.
11. A computer-implemented method, comprising: initializing a plurality of Central Processing Unit (CPU) circuits within a multi-core processor of an Information Handling System (IHS), wherein each of the CPU circuits comprises at least a core and an electronic circuit associated with the core, and wherein each electronic circuit includes at least one of: a memory controller or an input/output (I/O) lane; prior to the IHS booting an Operating System (OS), reporting an electronic circuit of a first core of a first CPU circuit as belonging to a second core of a second CPU circuit, wherein the electronic circuit includes an I/O extender local to the first core of the first CPU circuit; and modifying Advanced Configuration and Power Interface (ACPI) proximity (PXM) information to report one or more Peripheral Component Interconnect Express (PCIe) root ports local to the first core of the first CPU circuit as logical PCIe root ports local to the second core of the second CPU circuit.
A computer-implemented method involves initializing multiple CPU circuits within a multi-core processor. Each CPU circuit has a core and either a memory controller or I/O lane. Before the OS boots, the method reports a memory controller or I/O lane of a first CPU's core as belonging to a second CPU's core; this circuit functions as an I/O extender for the first core. Additionally, the method modifies ACPI PXM information to present PCIe root ports associated with the first core of the first CPU as logical PCIe root ports belonging to the second core of the second CPU.
12. The computer-implemented method of claim 11 , wherein the electronic circuit includes a memory controller local to the first core of the first CPU circuit.
The computer-implemented method of reporting a memory controller or I/O lane of a first CPU's core as belonging to a second CPU's core, and modifying ACPI PXM to remap PCIe root ports, specifically involves the electronic circuit that is remapped being a memory controller local to the first core of the first CPU. Thus, the memory controller is reassigned, along with remapping the associated PCIe ports.
13. The computer-implemented method of claim 12 , further comprising creating or modifying a Local Advanced Programmable Interrupt Controller (LAPIC) table of an Advanced Configuration and Power Interface (ACPI), wherein the LAPIC table is configured to identify the second core of the second CPU circuit, and wherein the LAPIC table is configured not to identify the first core of the first CPU circuit.
The computer-implemented method of reporting a memory controller or I/O lane of a first CPU's core as belonging to a second CPU's core, modifying ACPI PXM to remap PCIe root ports, further includes creating or modifying an ACPI LAPIC table. This table identifies the second core of the second CPU but does not identify the first core of the first CPU, effectively hiding the first core's existence and routing interrupts to the second core.
14. The computer-implemented method of claim 13 , further comprising creating or modifying an Advanced Configuration and Power Interface (ACPI) Static Resource Affinity Table (SRAT) to identify the memory controller as being coupled directly to the second core of the second CPU circuit.
The computer-implemented method of reporting a memory controller or I/O lane of a first CPU's core as belonging to a second CPU's core, modifying ACPI PXM to remap PCIe root ports, and creating/modifying the LAPIC table, also includes creating or modifying an ACPI SRAT table. This SRAT table is modified to identify the memory controller from the first core of the first CPU as being directly connected to the second core of the second CPU, defining the memory affinity.
15. The computer-implemented method of claim 14 , further comprising creating or modifying an Advanced Configuration and Power Interface (ACPI) System Locality Information Table (SLIT) to identify the memory controller as including a remote memory coupled to the second core of the second CPU circuit.
The computer-implemented method of reporting a memory controller or I/O lane of a first CPU's core as belonging to a second CPU's core, modifying ACPI PXM to remap PCIe root ports, creating/modifying the LAPIC table, and creating/modifying the SRAT table, further includes creating or modifying an ACPI SLIT table. This table is modified to identify the memory controller as including a remote memory coupled to the second core of the second CPU, reflecting the inter-CPU memory access latency.
16. The computer-implemented method of claim 11 , further comprising, in response to a System Management Mode (SMM) of operation being invoked to address a memory or I/O error of the first core of the first CPU circuit during Operating System (OS) runtime, reporting the error as having been originated by the second core of the second CPU circuit.
The computer-implemented method of reporting a memory controller or I/O lane of a first CPU's core as belonging to a second CPU's core, modifying ACPI PXM to remap PCIe root ports, addresses error handling. If an SMM operation is invoked due to a memory or I/O error from the first core of the first CPU during OS runtime, the method reports that the error originated from the second core of the second CPU. This provides a level of abstraction for error handling.
17. A hardware memory device having program instructions stored thereon that, upon execution by an Information Handling System (IHS), cause the IHS to: initialize a plurality of Central Processing Unit (CPU) circuits, wherein each of the CPU circuits comprises at least a core and a memory controller; create or modify a Local Advanced Programmable Interrupt Controller (LAPIC) table of an Advanced Configuration and Power Interface (ACPI), wherein the LAPIC table is configured to identify a second core of a second CPU circuit, and wherein the LAPIC table is configured not to identify a first core of a first CPU circuit; create or modify an ACPI Static Resource Affinity Table (SRAT) to identify a memory controller corresponding to the first core of the first CPU circuit as belonging to the second core of the second CPU circuit; create or modify an ACPI System Locality Information Table (SLIT) to identify the memory controller as including a remote memory coupled to the second core of the second CPU circuit; and in response to a System Management Mode (SMM) of operation being invoked to address a memory or I/O error of the first core of the first CPU circuit during Operating System (OS) runtime, identifying the error as having been originated by the second core of the second CPU circuit.
A hardware memory device stores program instructions. When executed by an IHS, these instructions initialize multiple CPU circuits, each with a core and memory controller. The instructions create/modify an ACPI LAPIC table identifying a second core of a second CPU but not a first core of a first CPU. An ACPI SRAT table is created/modified, assigning the memory controller of the first core to the second core. The ACPI SLIT table is updated to show the memory controller as remote memory for the second core. Finally, in SMM mode during OS runtime, memory or I/O errors from the first core are attributed to the second core.
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January 25, 2015
August 15, 2017
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