A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory module comprising: a set of first memory devices, each of the first memory devices including a command-input port and a data port, wherein the first memory devices are variable-data-width memory devices; a set of second memory devices, each of the second memory devices including a command-input port and a data port; a set of third memory devices, each of the third memory devices including a command-input port and a data port; a set of fourth memory devices, each of the fourth memory devices including a command-input port and a data port; and a command buffer having: a first command-output port coupled to the command-input port of the first memory devices; a second command-output port coupled to the command-input port of the second memory devices; a third command-output port coupled to the command-input port of the third memory devices; a fourth command-output port coupled to the command-input port of the fourth memory devices; at least one module command port; and logic to alternatively direct commands from the at least one module command port to alternative sets of the set of first memory devices, the set of second memory devices, the set of third memory devices, and the set of fourth memory devices.
A memory module has four sets of memory devices. Each memory device in each set has a command input port and a data port and can have a programmable data width. A command buffer directs commands to these memory devices. The command buffer has four output ports, each connected to one of the four sets of memory devices. The command buffer also has one or more module command input ports and can direct commands received on these input ports to different sets of memory devices, effectively routing commands as needed.
2. The memory module of claim 1 , wherein the second memory devices, the third memory devices, and the fourth memory devices are identical to the first memory devices.
The memory module described above, where the second, third, and fourth sets of memory devices are identical to the first set of memory devices, meaning all the memory devices are the same type.
3. The memory module of claim 1 , wherein the first memory devices each include first and second device data ports.
The memory module described above, where the first set of memory devices each includes two data ports, enabling each device to transfer data through two independent channels.
4. The memory module of claim 3 , wherein the first device data port is of a data width, and the second device data port is of the data width.
The memory module with memory devices each containing first and second data ports, where the first and second data ports on each memory device in the first set have the same data width, supporting parallel data access.
5. The memory module of claim 1 , wherein each of the sets of memory devices comprises multiple memory devices.
The memory module described above, where each of the four sets of memory devices contains multiple individual memory devices working together.
6. The memory module of claim 1 , wherein the logic includes first and second buffer command ports coupled to the at least one module command port, a multiplexer having first and second multiplexer input ports coupled to the first and second buffer command ports, and a multiplexer output coupled to one of the set of first memory devices and the set of second memory devices.
The memory module from above includes first and second buffer command ports connected to the module command input port. A multiplexer takes input from these two buffer command ports and selects one to output to either the first set of memory devices or the second set of memory devices. This enables selectively routing commands to either the first or second set.
7. The memory module of claim 6 , wherein the second multiplexer input port is coupled to the other of the set of first memory devices and the set of second memory devices.
The memory module with the multiplexer routing commands includes a setup where the multiplexer's two possible outputs connect to the first and second sets of memory devices respectively, so the multiplexer chooses between sending commands to the first or second memory set.
8. The memory module of claim 6 , the multiplexer having a select port, the memory module further comprising a programmable register coupled to the select port.
The memory module with the multiplexer has a selection port on the multiplexer, and a programmable register is connected to this selection port. By programming this register, the command routing can be dynamically altered.
9. The memory module of claim 6 , wherein the logic includes third and fourth buffer command ports coupled to the at least one module command port, a second multiplexer having third and fourth multiplexer input ports coupled to the third and fourth buffer command ports, and a second multiplexer output coupled to one of the set of third memory devices and the set of fourth memory devices.
The memory module with a multiplexer to direct command includes third and fourth buffer command ports also connected to the module command input port. A second multiplexer takes input from the third and fourth buffer command ports and selects one to output to either the third set of memory devices or the fourth set of memory devices.
10. The memory module of claim 9 , wherein the fourth multiplexer input port is coupled to the other of the set of third memory devices and the set of fourth memory devices.
In the memory module containing the second multiplexer as described in claim 9, the second multiplexer’s two possible outputs connect to the third and fourth sets of memory devices respectively.
11. A memory command buffer for communicating between a processing unit and sets of memory devices, including first, second, third, and fourth sets of the memory devices, the command buffer comprising: a first command-output port coupled to the memory devices of the first set of the memory devices; a second command-output port coupled to the memory devices of the second set of the memory devices; a third command-output port coupled to the memory devices of the third set of the memory devices; a fourth command-output port coupled to the memory devices of the fourth set of the memory devices; at least one module command port; and logic to alternatively direct commands from the at least one module command port to alternative collections of the first, second, third, and fourth sets of the memory devices via the respective first, second, third, and fourth command output ports; wherein the at least one module command port includes first and second module command ports, the command buffer to direct the commands from the first and second module command ports to the first and second command-output ports in a first configuration, and to direct the commands from the second module command port to the first and second command-output ports in a second configuration.
A memory command buffer communicates between a processor and four sets of memory devices. The buffer has four output ports, each connected to one of the sets of memory devices. It also has at least one (or more) module command input port. The buffer directs commands from the module command input port to different combinations of the memory device sets. Specifically, it has two module command input ports. In a first configuration, commands from both input ports are sent to the first and second set of memory devices. In a second configuration, only commands from the second input port are sent to the first and second set of memory devices.
12. The memory command buffer of claim 11 , further comprising a programmable register to store a value indicative of one of the first and second configurations.
The memory command buffer described above includes a programmable register. The value stored in this register determines which of the two configurations (first or second) is active, allowing dynamic reconfiguration of the command routing.
13. The memory command buffer of claim 11 , wherein the at least one module command port further includes third and fourth module command ports, the command buffer to direct the commands from the third and fourth module command ports to the third and fourth command-output ports in the first configuration, and to direct the commands from the third module command port to the third and fourth command-output ports in the second configuration.
The memory command buffer can contain four module command input ports. In the first configuration, commands from the third and fourth input ports are sent to the third and fourth sets of memory devices. In the second configuration, commands from only the third input port are sent to the third and fourth sets of memory devices.
14. A computer system comprising: a processing unit; a memory-module connector communicatively coupled to the processing unit to receive memory commands and data; and a memory module fixed to the connector to receive the memory commands and data, the memory module including: first, second, third, and fourth sets of memory devices, each memory device including a data port and a command-input port; and a command buffer having: first, second, third, and fourth command-output ports each coupled to the memory coupled to the command-input ports of the memory devices of the respective first, second, third, and fourth sets of memory devices; at least one module command port; and logic to alternatively direct commands from the at least one module command port to alternative combinations of the first, second, third, and fourth sets of memory devices; wherein the at least one module command port includes first and second module command ports, the command buffer to direct the commands from the first and second module command ports to the first and second command-output ports in a first configuration, and to direct the commands from the second module command port to the first and second command-output ports in a second configuration.
A computer system with a processor connected to a memory module via a connector. The memory module contains four sets of memory devices. A command buffer directs commands to these memory devices, with an output port for each set. The buffer can route commands received on its input ports to different combinations of the sets. The memory buffer has first and second module command input ports; it directs commands from the first and second input ports to the first and second command output ports in a first configuration, and directs commands from the second input port to the first and second command output ports in a second configuration.
15. The computer system of claim 14 , further comprising a mode memory to select between first and second configurations.
The computer system includes a memory (called the mode memory) that stores configuration information to select either the first or second command routing configuration.
16. The computer system of claim 14 , wherein the at least one module command port includes third and fourth module command ports, the command buffer to direct the commands from the third and fourth module command ports to the third and fourth command-output ports in the first configuration, and to direct the commands from the third module command port to the third and fourth command-output ports in the second configuration.
The computer system can contain four module command input ports. The command buffer directs commands from the third and fourth input ports to the third and fourth command output ports in a first configuration, and directs commands from the third input port to the third and fourth command output ports in a second configuration.
17. The computer system of claim 16 , wherein the memory module communicates the data at a first data width in the first configuration and at a second data width in the second configuration.
The computer system is configured to operate with different data widths depending on the selected configuration (first or second). In the first configuration, the system communicates data at a first data width; in the second configuration, it communicates data at a second, potentially different, data width.
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February 23, 2016
August 15, 2017
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