A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in a selection region of a semiconductor substrate. The keep out zone may be configured to define a peripheral region of the TSV. The dummy patterns may be arranged in the keep out zone to receive a conductive signal. The dummy patterns may function as an electrode of a reservoir capacitor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor integrated circuit device comprising: a semiconductor substrate defining a bank group area and a peripheral circuit region; a keep out zone positioned in the peripheral circuit region; a through silicon via (TSV) arranged in the keep out zone; an isolation region configured to surround the TSV; and a plurality of dummy patterns arranged in the keep out zone outside of the isolation region, to receive a conductive signal.
2. The semiconductor integrated circuit device of claim 1 , wherein the TSV is electrically isolated from the dummy patterns by the isolation region.
3. The semiconductor integrated circuit device of claim 1 , further comprising a plurality of power mesh lines electrically connected to the dummy patterns.
4. The semiconductor integrated circuit device of claim 3 , wherein the dummy patterns extend in a direction substantially parallel to an extending direction of at least some of the power mesh lines.
5. The semiconductor integrated circuit device of claim 4 , wherein the power mesh lines are electrically isolated from each other.
6. The semiconductor integrated circuit device of claim 1 , wherein each of the dummy patterns has a frame shape.
7. The semiconductor integrated circuit device of claim 1 , wherein the TSV is arranged in a peripheral circuit region of the semiconductor substrate.
8. The semiconductor integrated circuit device of claim 1 , wherein the dummy patterns comprises a conductive material substantially the same as a conductive material of a gate of a transistor.
9. The electronic system of claim 1 , wherein the dummy patterns function as an electrode of a reservoir capacitor.
10. The semiconductor integrated circuit device of claim 3 , wherein at least one of power mesh lines is configured to be substantially perpendicular to the dummy patterns.
11. The semiconductor integrated circuit device of claim 3 , wherein the at least one power mesh line is substantially parallel with and perpendicular to sides of the dummy pattern.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 26, 2016
August 22, 2017
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