A semiconductor device includes a first power rail, a second power rail, at least one standard cell and at least one power bridge. The first power rail extends in a first direction over a substrate. The second power rail extends in the first direction over the substrate, and the second power rail is spaced apart from the first power rail in a second direction that intersects the first direction. The at least one standard cell receives a first voltage from the first and the second power rails. The at least one power bridge connects the first power rail and the second power rail in the second direction. The first power rail and the second power rail are formed in a first metal layer and the least one power bridge is formed in a bottom metal layer that is under the first metal layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a first power rail extending in a first direction over a substrate having a first conductive type; a second power rail extending in the first direction over the substrate, the second power rail being spaced apart from the first power rail by a predetermined distance in a second direction that intersects the first direction; at least one standard cell receiving a first voltage from the first power rail and the second power rail; and at least one power bridge configured to connect the first power rail and the second power rail in the second direction within the at least one standard cell, wherein the first power rail and the second power rail are formed in a first metal layer and the least one power bridge is formed in a bottom metal layer that is under the first metal layer, and wherein the at least one standard cell has a cell boundary defined by the first power rail and the second power rail.
2. The semiconductor device of claim 1 , further comprising: a third power rail extending in the first direction between the first power rail and the second power rail, wherein the third power rail is formed in the first metal layer and the third power rail provides a second voltage different from the first voltage.
3. The semiconductor device of claim 2 , further comprising: at least one first branch portion protruding from the first power rail toward the third power rail, the at least one first branch portion extending in the second direction such that the at least one first branch portion is spaced apart from the third power rail in the second direction; and at least one second branch portion protruding from the second power rail toward the third power rail, the at least one second branch portion extending in the second direction such that the at least one second branch portion is spaced apart from the third power rail in the second direction.
4. The semiconductor device of claim 3 , wherein each width of the at least one first branch portion and the at least one second branch portion is substantially the same as a width of the at least one power bridge.
5. The semiconductor device of claim 4 , wherein: the at least one power bridge includes a first power bridge and a second power bridge that are spaced apart from each other in the first direction; the at least one first branch portion includes a first branch portion and a second branch portion that are spaced apart from each other in the first direction; and the at least one second branch portion includes a third branch portion and a fourth branch portion that are spaced apart from each other in the first direction.
6. The semiconductor device of claim 3 , wherein each width of the at least one first branch portion and the at least one second branch portion is greater than a width of the at least one power bridge.
7. The semiconductor device of claim 3 , wherein the at least one first branch portion is connected to the at least one power bridge through a first contact, the at least one second branch portion is connected to the at least one power bridge through a second contact, and the at least one first branch portion and the at least one second branch portion reduce a resistance of the at least one power bridge.
8. The semiconductor device of claim 1 , further comprising: a first well formed in the substrate, the first well having a second conductive type; and a second well formed in the substrate separately from the first well, the second well having the second conductive type, wherein the first power rail is formed over the first well, and the second power rail is formed over the second well.
9. The semiconductor device of claim 8 , wherein the first conductive type is p-type and the second conductive type is n-type.
10. The semiconductor device of claim 8 , further comprising: a first impurity region formed in the first well within the standard cell; a second impurity region formed in the second well within the standard cell; and a gate electrode crossing the first impurity region and the second impurity region in the second direction.
11. The semiconductor device of claim 10 , wherein the at least one power bridge partially overlaps with the gate electrode in a third direction orthogonal to the first direction and the second direction, the at least one power bridge being formed higher than the gate electrode in the third direction.
12. The semiconductor device of claim 10 , wherein the first impurity region, the second impurity region and the gate electrode constitute a plurality of transistors, and the plurality of transistors operate as a decoupling capacitor.
13. A semiconductor device, comprising: a first power rail extending in a first direction over a substrate in a first metal layer; a second power rail extending in the first direction over the substrate in the first metal layer, the second power rail being spaced apart from the first power rail in a second direction that intersects with the first direction; a third power rail extending in the first direction over the substrate between the first power rail and the second power rail; and at least one power bridge extending in the second direction in a second metal layer below the first metal layer and configured to connect the first and second power rails in at least one standard cell, wherein the at least one standard cell has a cell boundary defined by the first power rail and the second power rail and receives a first voltage from the first power rail and the second power rail.
14. The semiconductor device of claim 13 , wherein the third power rail is formed in the first metal layer and the third power rail provides a second voltage different from the first voltage.
15. The semiconductor device of claim 13 , further comprising: at least one first branch portion protruding from the first power rail toward the third power rail, the at least one first branch portion extending in the second direction such that the at least one first branch portion is spaced apart from the third power rail in the second direction; and at least one second branch portion protruding from the second power rail toward the third power rail, the at least one second branch portion extending in the second direction such that the at least one second branch portion is spaced apart from the third power rail in the second direction.
16. The semiconductor device of claim 13 , further comprising: a first well formed in the substrate having a first conductive type, the first well having a second conductive type; and a second well formed in the substrate separately from the first well, the second well having the second conductive type, wherein the first power rail is formed over the first well, and the second power rail is formed over the second well.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 2, 2016
September 5, 2017
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