A semiconductor device includes a first power rail, a second power rail, at least one standard cell and at least one power bridge. The first power rail extends in a first direction over a substrate. The second power rail extends in the first direction over the substrate, and the second power rail is spaced apart from the first power rail in a second direction that intersects the first direction. The at least one standard cell receives a first voltage from the first and the second power rails. The at least one power bridge connects the first power rail and the second power rail in the second direction. The first power rail and the second power rail are formed in a first metal layer and the least one power bridge is formed in a bottom metal layer that is under the first metal layer.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device, comprising: a first power rail extending in a first direction over a substrate having a first conductive type; a second power rail extending in the first direction over the substrate, the second power rail being spaced apart from the first power rail by a predetermined distance in a second direction that intersects the first direction; at least one standard cell receiving a first voltage from the first power rail and the second power rail; and at least one power bridge configured to connect the first power rail and the second power rail in the second direction within the at least one standard cell, wherein the first power rail and the second power rail are formed in a first metal layer and the least one power bridge is formed in a bottom metal layer that is under the first metal layer, and wherein the at least one standard cell has a cell boundary defined by the first power rail and the second power rail.
A semiconductor device includes a substrate and two power rails (first and second) running in the same direction on top of it. These power rails are separated by a specific distance. Standard cells within the device receive power from these rails. Power bridges, located in a lower metal layer beneath the power rails, connect the first and second power rails inside these standard cells. The standard cell has boundaries defined by the location of the first and second power rails.
2. The semiconductor device of claim 1 , further comprising: a third power rail extending in the first direction between the first power rail and the second power rail, wherein the third power rail is formed in the first metal layer and the third power rail provides a second voltage different from the first voltage.
The semiconductor device from the previous description also includes a third power rail between the first and second power rails. This third power rail is also in the same (first) metal layer as the first and second power rails. This third power rail provides a different voltage than the voltage provided by the first and second power rails.
3. The semiconductor device of claim 2 , further comprising: at least one first branch portion protruding from the first power rail toward the third power rail, the at least one first branch portion extending in the second direction such that the at least one first branch portion is spaced apart from the third power rail in the second direction; and at least one second branch portion protruding from the second power rail toward the third power rail, the at least one second branch portion extending in the second direction such that the at least one second branch portion is spaced apart from the third power rail in the second direction.
The semiconductor device with three power rails, as described previously, includes branch portions extending from the first and second power rails towards the third power rail. These branch portions do not touch the third power rail; there's a gap between them. The first branch portion extends from the first power rail, and the second branch portion extends from the second power rail.
4. The semiconductor device of claim 3 , wherein each width of the at least one first branch portion and the at least one second branch portion is substantially the same as a width of the at least one power bridge.
In the semiconductor device with power rails and branch portions as previously described, the width of each branch portion extending from the first and second power rails is approximately the same as the width of the power bridges connecting the first and second power rails in the bottom metal layer.
5. The semiconductor device of claim 4 , wherein: the at least one power bridge includes a first power bridge and a second power bridge that are spaced apart from each other in the first direction; the at least one first branch portion includes a first branch portion and a second branch portion that are spaced apart from each other in the first direction; and the at least one second branch portion includes a third branch portion and a fourth branch portion that are spaced apart from each other in the first direction.
In the semiconductor device described with matching branch and power bridge widths, there are multiple power bridges (a first and second) spaced apart. Correspondingly, there are multiple branch portions on the first power rail (a first and second) spaced apart, and multiple branch portions on the second power rail (a third and fourth) spaced apart. These branch portions align with the multiple power bridges.
6. The semiconductor device of claim 3 , wherein each width of the at least one first branch portion and the at least one second branch portion is greater than a width of the at least one power bridge.
In the semiconductor device with three power rails as described previously, the width of each branch portion extending from the first and second power rails is wider than the width of the power bridges connecting the first and second power rails in the bottom metal layer.
7. The semiconductor device of claim 3 , wherein the at least one first branch portion is connected to the at least one power bridge through a first contact, the at least one second branch portion is connected to the at least one power bridge through a second contact, and the at least one first branch portion and the at least one second branch portion reduce a resistance of the at least one power bridge.
In the semiconductor device with three power rails and branch portions described above, each branch portion connects to a power bridge via a contact. These branch portions are designed to reduce the electrical resistance of the power bridges. Specifically, the branch from the first power rail connects to the power bridge using a first contact, and the branch from the second power rail connects to the same power bridge using a second contact.
8. The semiconductor device of claim 1 , further comprising: a first well formed in the substrate, the first well having a second conductive type; and a second well formed in the substrate separately from the first well, the second well having the second conductive type, wherein the first power rail is formed over the first well, and the second power rail is formed over the second well.
The semiconductor device includes a substrate, a first well with a specific conductivity type, and a second well (separate from the first) with the same conductivity type. The first power rail is located over the first well, and the second power rail is located over the second well.
9. The semiconductor device of claim 8 , wherein the first conductive type is p-type and the second conductive type is n-type.
In the semiconductor device with wells, the first well is p-type, and the second well is n-type. The first power rail is over the p-type well, and the second power rail is over the n-type well.
10. The semiconductor device of claim 8 , further comprising: a first impurity region formed in the first well within the standard cell; a second impurity region formed in the second well within the standard cell; and a gate electrode crossing the first impurity region and the second impurity region in the second direction.
The semiconductor device with wells and power rails features impurity regions within each well. There is a first impurity region in the first well and a second impurity region in the second well, both located inside a standard cell. A gate electrode crosses both impurity regions.
11. The semiconductor device of claim 10 , wherein the at least one power bridge partially overlaps with the gate electrode in a third direction orthogonal to the first direction and the second direction, the at least one power bridge being formed higher than the gate electrode in the third direction.
In the semiconductor device with wells, impurity regions, and a gate electrode as previously described, the power bridges (which connect the first and second power rails) partially overlap the gate electrode when viewed from above. The power bridges are located at a higher layer than the gate electrode.
12. The semiconductor device of claim 10 , wherein the first impurity region, the second impurity region and the gate electrode constitute a plurality of transistors, and the plurality of transistors operate as a decoupling capacitor.
The semiconductor device with wells, impurity regions, and a gate electrode as previously described, forms transistors which act as a decoupling capacitor. The first and second impurity regions, along with the gate electrode, create this capacitive effect to reduce voltage noise.
13. A semiconductor device, comprising: a first power rail extending in a first direction over a substrate in a first metal layer; a second power rail extending in the first direction over the substrate in the first metal layer, the second power rail being spaced apart from the first power rail in a second direction that intersects with the first direction; a third power rail extending in the first direction over the substrate between the first power rail and the second power rail; and at least one power bridge extending in the second direction in a second metal layer below the first metal layer and configured to connect the first and second power rails in at least one standard cell, wherein the at least one standard cell has a cell boundary defined by the first power rail and the second power rail and receives a first voltage from the first power rail and the second power rail.
A semiconductor device includes a substrate, a first power rail in a first metal layer, and a second power rail in the same first metal layer, running parallel to the first power rail. A third power rail also runs parallel between the first and second. Power bridges in a second metal layer (below the first) connect the first and second power rails within at least one standard cell. The standard cell boundaries are defined by the first and second power rails, and the standard cell receives power from the first and second power rails.
14. The semiconductor device of claim 13 , wherein the third power rail is formed in the first metal layer and the third power rail provides a second voltage different from the first voltage.
In the semiconductor device with three power rails in the first metal layer as described previously, the third power rail provides a different voltage than the voltage provided by the first and second power rails.
15. The semiconductor device of claim 13 , further comprising: at least one first branch portion protruding from the first power rail toward the third power rail, the at least one first branch portion extending in the second direction such that the at least one first branch portion is spaced apart from the third power rail in the second direction; and at least one second branch portion protruding from the second power rail toward the third power rail, the at least one second branch portion extending in the second direction such that the at least one second branch portion is spaced apart from the third power rail in the second direction.
The semiconductor device with three power rails, as described previously, includes branch portions extending from the first and second power rails towards the third power rail. These branch portions do not touch the third power rail; there's a gap between them. The first branch portion extends from the first power rail, and the second branch portion extends from the second power rail.
16. The semiconductor device of claim 13 , further comprising: a first well formed in the substrate having a first conductive type, the first well having a second conductive type; and a second well formed in the substrate separately from the first well, the second well having the second conductive type, wherein the first power rail is formed over the first well, and the second power rail is formed over the second well.
The semiconductor device includes a substrate, a first well with a specific conductivity type, and a second well (separate from the first) with a the same conductivity type. The first power rail is located over the first well, and the second power rail is located over the second well.
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March 2, 2016
September 5, 2017
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