A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.
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1. A method for forming a via in an integrated circuit, the method comprising: patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer; removing an exposed portion of the first OPL layer to define a cavity; removing an exposed portion of a second hardmask disposed under the first OPL layer to further define the cavity; removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity; removing an exposed portion of a first cap layer disposed under the first dielectric layer to further define the cavity; removing an exposed portion of a second dielectric layer disposed under the first cap layer to further define to further define the cavity; removing an exposed portion of a second cap layer disposed under the second dielectric layer to further define to further define the cavity; removing an exposed portion of a liner layer over a second conductive material in the cavity; and depositing a conductive material in the cavity.
A method for creating a via (a vertical connection) in an integrated circuit involves several steps. First, a pattern is etched into a hardmask layer that sits on top of a self-planarizing polymer (OPL) layer. Then, the exposed OPL is removed, forming a cavity. Next, exposed sections of a second hardmask layer (located below the OPL) are removed, further deepening the cavity. This process continues by removing exposed portions of a dielectric layer, a cap layer, another dielectric layer, and another cap layer, each located successively lower in the structure, enlarging the cavity at each step. Finally, after removing an exposed liner layer over a conductive material, the cavity is filled with a conductive material to form the via.
2. The method of claim 1 , further comprising depositing a single layer of liner material in the cavity prior to depositing a conductive material in the cavity.
The method for creating a via in an integrated circuit, which includes patterning a hardmask on a self-planarizing polymer (OPL) layer, removing the exposed OPL to create a cavity, and sequentially removing layers (hardmask, dielectric, cap layers) to expose a conductive material for via formation, also includes depositing a single layer of liner material inside the cavity before filling it with a conductive material. This liner layer improves the electrical contact and adhesion between the conductive via fill and the underlying conductive material.
3. The method of claim 1 , wherein the first hardmask includes a titanium nitride (TiN) layer and an oxide material layer disposed between the TiN layer and the first OPL layer.
In the method for creating a via in an integrated circuit, which involves patterning a hardmask on a self-planarizing polymer (OPL) layer, removing the exposed OPL to create a cavity, and sequentially removing layers (hardmask, dielectric, cap layers) to expose a conductive material for via formation, the first hardmask (the one patterned initially) is composed of two layers: a titanium nitride (TiN) layer on top and an oxide material layer between the TiN layer and the OPL layer. The oxide layer improves adhesion and etching selectivity.
4. The method of claim 1 , wherein the removing the exposed portion of the first OPL layer to define a cavity is performed by a reactive ion etching (RIE) process that is selective to TiN material.
In the method for creating a via in an integrated circuit, which involves patterning a hardmask on a self-planarizing polymer (OPL) layer, removing the exposed OPL to create a cavity, and sequentially removing layers (hardmask, dielectric, cap layers) to expose a conductive material for via formation, the step of removing the exposed OPL to form the cavity is done using a reactive ion etching (RIE) process. This RIE process is specifically designed to remove the OPL material without significantly etching titanium nitride (TiN) that may be present in an underlying hardmask layer.
5. The method of claim 1 , wherein the removing the exposed portion of the first OPL layer to define a cavity is performed by a reactive ion etching (RIE) process that is selective to TiN and oxide materials.
In the method for creating a via in an integrated circuit, which involves patterning a hardmask on a self-planarizing polymer (OPL) layer, removing the exposed OPL to create a cavity, and sequentially removing layers (hardmask, dielectric, cap layers) to expose a conductive material for via formation, the step of removing the exposed OPL to define the cavity uses reactive ion etching (RIE). This RIE process is selective, meaning it removes the OPL much faster than it removes both titanium nitride (TiN) and oxide materials. This ensures the OPL is removed cleanly without damaging underlying layers made of TiN or oxide.
6. The method of claim 1 , wherein the second hardmask includes an oxide material.
In the method for creating a via in an integrated circuit, which involves patterning a hardmask on a self-planarizing polymer (OPL) layer, removing the exposed OPL to create a cavity, and sequentially removing layers (hardmask, dielectric, cap layers) to expose a conductive material for via formation, the second hardmask (the one below the OPL) is made of an oxide material. This oxide layer provides a masking function during subsequent etching steps.
7. The method of claim 1 , wherein the second hardmask includes a nitride material.
In the method for creating a via in an integrated circuit, which involves patterning a hardmask on a self-planarizing polymer (OPL) layer, removing the exposed OPL to create a cavity, and sequentially removing layers (hardmask, dielectric, cap layers) to expose a conductive material for via formation, the second hardmask (the one below the OPL) is made of a nitride material. This nitride layer acts as an etch stop or mask during subsequent processing steps.
8. The method of claim 1 , wherein the second cap layer is a nitride.
Semiconductor fabrication. This invention addresses the need for improved semiconductor device performance and reliability by providing a specific material for a cap layer. A semiconductor structure includes a substrate, a channel region formed on the substrate, and a gate electrode positioned above the channel region. A first cap layer is disposed between the channel region and the gate electrode. A second cap layer is positioned above the first cap layer and below the gate electrode. This second cap layer is specifically a nitride material. The method involves forming these layers in a sequence to create the described structure. The use of a nitride as the second cap layer is intended to enhance the electrical properties and stability of the semiconductor device.
9. The method of claim 8 , wherein the nitride is chosen from the group consisting of silicon nitride, silicon carbon nitride, or silicon oxynitride.
The method for creating a via in an integrated circuit, involving the use of a patterned hardmask, removal of OPL and sequential removal of layers to expose a conductive material, includes a second cap layer composed of a nitride material, where this nitride can be silicon nitride, silicon carbon nitride, or silicon oxynitride. These materials provide insulation and etch stop functionality, and offer different electrical and etching characteristics.
10. The method of claim 1 , wherein the second cap layer is an oxide.
In the method for creating a via in an integrated circuit, which involves patterning a hardmask on a self-planarizing polymer (OPL) layer, removing the exposed OPL to create a cavity, and sequentially removing layers (hardmask, dielectric, cap layers) to expose a conductive material for via formation, the second cap layer (one of the layers removed to form the cavity) is an oxide material. This oxide layer provides electrical insulation and/or serves as an etch stop.
11. The method of claim 1 , wherein the second cap layer is a silicon oxide.
In the method for creating a via in an integrated circuit, which involves patterning a hardmask on a self-planarizing polymer (OPL) layer, removing the exposed OPL to create a cavity, and sequentially removing layers (hardmask, dielectric, cap layers) to expose a conductive material for via formation, the second cap layer (one of the layers removed to form the cavity) is specifically silicon oxide. Silicon oxide provides electrical insulation and can be selectively etched during via formation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 12, 2016
September 19, 2017
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