Synchronized semiconductor device with phase adjustment circuit

1. An apparatus, comprising: a pulse width detection circuit configured to determine whether each of a plurality of step sizes is less than at least one of a high pulse width and a low pulse width of a first clock signal and select a first step size, wherein the pulse width detection circuit comprises: a first flip-flop configured to output a first test signal responsive to one of a rising and a falling edge of the first clock signal; a first delay circuit coupled to the first flip-flop to receive the first test signal and configured to delay the first test signal by a second delay amount to produce a delayed first test signal, wherein the second delay amount being adjustable; and a second flip-flop coupled to the first delay circuit and configured to receive the delayed first test signal responsive to the other of the rising and the falling edge of the first clock signal; and a delay line configured to delay the first clock signal by a first delay amount to produce a second clock signal, the first delay amount being changed based at least on the first step size.

2. The apparatus of claim 1 , wherein the pulse width detection circuit is configured to produce step size information that indicates the first step size, the apparatus further comprises a delay line control circuit configured to receive the step size information and provide delay control information to the delay line responsive, at least in part, to the step size information, and wherein the delay line is configured to change the first delay amount responsive, at least in part, the delay control information.

3. The apparatus of claim 1 , wherein the pulse width detection circuit further comprises: a third flip-flop configured to output a second test signal responsive to the other of the rising and falling edges of the first clock signal; a second delay circuit coupled to the third flip-flop to receive the second test signal and configured to delay the second test signal to produce a delayed second test signal by the second delay amount; and a fourth flip-flop coupled to the second delay circuit and configured to receive the delayed second test signal responsive to the one of the rising and falling edges of the first clock signal.

4. The apparatus of claim 1 , wherein the first step size is the largest one among the plurality of step sizes that are less than the one of the high pulse width and the low pulse width of the first clock signal.

5. An apparatus comprising: a pulse width detection circuit configured to receive a first clock signal having an associated pulse width, and further configured to produce first information, the first information indicating that the associated pulse width is greater than or equal to an integer times an unitary delay amount and less than the integer plus one times the unitary delay amount, wherein the pulse width detection circuit comprises: a first flip-flop configured to output a first test signal responsive to one of a rising edge and a falling edge of the first clock signal; a first delay circuit configured to receive the first test signal and delay the first test signal to produce a delayed first test signal, the first delay circuit further configured to adjust a delay amount thereof to delay the first test signal by at least the integer times the unitary delay amount and the integer plus one times the unitary delay amount; and a second flip-flop configured to receive the delayed first test signal responsive to the other of the rising edge and the falling edge of the first clock signal.

6. The apparatus of claim 5 , further comprising: a delay line configured to receive the first clock signal and second information and to produce a second clock signal by delaying the first clock signal in response to the second information; and a delay line control circuit coupled to the pulse width detection circuit and the delay line and configured to change the second information responsive, at least in part, to the first information, the second information being changed such that a delay amount of the delay line is changed stepwise from a current value to a new value by an amount that substantially corresponds to the integer times the unitary delay amount.

7. The apparatus of claim 5 , wherein the pulse width detection circuit further comprises: a third flip-flop configured to output a second test signal responsive to the other of the rising edge and the falling edge of the first clock signal; a second delay circuit configured to receive the second test signal and delay the second delay signal to produce a delayed second test signal, the second delay circuit further configured to adjust a delay amount thereof to delay the second test signal by at least the integer times the unitary delay amount and the integer plus one times the unitary delay amount; and a fourth flip-flop configured to receive the delayed second test signal responsive to the one of the rising edge and the falling edge of the first clock signal.

8. The apparatus of claim 5 , wherein the pulse width detection circuit comprises a delay circuit that includes a plurality of sets of delay elements, each of the sets of delay element is configured to represent the unitary delay amount.

9. An apparatus, comprising: a pulse width detection circuit configured to receive a periodic clock signal, the pulse width detection circuit including a pulse width comparison circuit configured to compare each of a plurality of delay step sizes to one of a high and a low pulse width of the periodic clock signal to determine an acceptable step size, wherein the pulse width comparison circuit comprises: a rising edge flip-flop configured to receive the periodic clock signal and an input signal; one of an adjustable delay circuit or a fixed delay circuit coupled to the rising edge flip-flop; and a falling edge flip-flop coupled to the adjustable delay circuit and configured to receive the periodic clock signal; and a delay locked loop circuit, coupled to the pulse width detection circuit, configured to step the periodic clock signal responsive, at least in part, to the acceptable step size.

10. The apparatus of claim 9 , wherein the fixed delay circuit is configured to provide one or more output signals, each output signal corresponding to a different delay step size.

11. The apparatus of claim 9 , wherein the acceptable step size is the largest one among the plurality of step sizes that are less than the one of high and low pulse widths of the clock signal.

12. A method comprising: receiving, at a rising edge flip flop, a test signal; providing, by the rising edge flip flop, the test signal to a delay circuit responsive to a rising edge or a falling edge of a first clock signal; providing, by the delay circuit, a plurality of delayed test signals indicative of possible step sizes to a plurality of falling edge flip flops; comparing each of the plurality delayed test signals with a high pulse width of the first clock signal to select one of the plurality of step sizes; and producing a second clock signal by delaying the first clock signal by a delay amount that is changed in a step-wise fashion responsive to the selected one of the plurality step size.

13. The method of claim 12 , further comprising: comparing each of the plurality of step sizes with a low pulse width of the first clock signal to select the one of the plurality of step sizes.

14. The method of claim 13 , wherein the one of the plurality of step sizes is the largest one among the plurality of step sizes that are less than both of the high and low pulse widths of the first clock signal.

15. The method of claim 12 , wherein each of the plurality of step sizes is greater than or equal to an integer times an unitary delay amount.

16. The method of claim 12 , further comprising: comparing the first and second clock signals to determine whether the first and second periodic clock signals are synchronized.