A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile memory device comprising: a three-dimensional memory cell array; a plurality of page buffers connected to the memory cell array through bit lines; and a pipeline output stage connected to the plurality of page buffers through data lines, wherein the pipeline output stage comprises: a plurality of first pipeline output stages each including a plurality of first registers connected to the plurality of page buffers in a wave pipeline architecture; a data multiplexer connected to each of the plurality of first pipeline output stages and configured to select and transmit data output from one of the plurality of first pipeline output stages; and at least one second pipeline output stage connected to an output of the data multiplexer in the wave pipeline architecture, the at least one second pipeline output stage including a plurality of second registers configured to store the data transmitted from the data multiplexer.
2. The nonvolatile memory device of claim 1 , further comprising: compare logics connected between the first pipeline output stages and the data multiplexer and configured to compare output data of the first pipeline output stages with expected data.
3. The nonvolatile memory device of claim 2 , wherein each of the compare logics checks integrity of data transmitted to at least one of the data lines.
4. The nonvolatile memory device of claim 2 , wherein the at least one second pipeline output stage is connected to input/output pads.
5. The nonvolatile memory device of claim 4 , wherein the plurality of second registers are disposed to be scattered at the input/output pads.
6. The nonvolatile memory device of claim 4 , wherein the plurality of second registers are disposed to be clustered at one of the input/output pads.
7. The nonvolatile memory device of claim 4 , further comprising: a second data multiplexer connected to the input/output pads and configured to receive data through data lines separated from registers of second pipeline output stages from among the at least one second pipeline output stage and transmit one of the received data to the input/output pads in response to a multiplexing control signal.
8. The nonvolatile memory device of claim 1 , further comprising: an internal clock generator configured to use an external clock to generate an internal clock during a time interval corresponding to a latency of the pipeline output stage.
9. The nonvolatile memory device of claim 8 , further comprising: at least one latency counter configured to count a latency of the internal clock; and a clock multiplexer configured to use one of output clocks from the first pipeline output stages as an input clock of the at least one second pipeline output stage.
10. The nonvolatile memory device of claim 8 , further comprising: a clock input selector configured to determine whether to provide the internal clock to one of the first pipeline output stages, based on an array selection signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 11, 2017
September 26, 2017
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