A via opening is provided in an interconnect dielectric material. Prior to line opening formation, a continuous layer of a sacrificial material is formed lining the entirety of the via opening. An organic planarization layer (OPL) and a photoresist that contains a line pattern are formed above the interconnect dielectric material. The line pattern is then transferred into an upper portion of the interconnect dielectric material, while maintaining a portion of the OPL and a portion of the continuous layer of sacrificial material within a lower portion of the via opening. The remaining portions of the OPL and the sacrificial material are then removed from the bottom portion of the via opening. A combined via opening/line opening is provided in which the via opening has a well controlled profile/geometry. An interconnect metal or metal alloy can then be formed into the combined via opening/line opening.
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1. A method of forming a semiconductor structure, said method comprising: forming a via opening in an interconnect dielectric material layer; forming a continuous layer of a sacrificial material lining the entirety of said via opening; forming a material stack comprising an organic planarization layer (OPL) and a patterned photoresist above said interconnect dielectric material layer, wherein a portion of said OPL fills a remaining volume of said via opening, and wherein said patterned photoresist contains a line pattern that is present directly above said via opening; transferring said line pattern to an upper portion of said interconnect dielectric material layer, wherein a portion of said OPL and a portion of said continuous layer of sacrificial material remain within a lower portion of the via opening after said transferring; removing said remaining portions of said OPL and said sacrificial material from said bottom portion of said via opening after said transferring to provide a combined via opening/line opening; and forming an interconnect metal or metal alloy within said combined via opening/line opening.
A method for creating interconnects in semiconductor devices involves first creating a via (a hole) in a dielectric material. The entire via is then lined with a continuous layer of a sacrificial material. Next, an organic planarization layer (OPL) and a patterned photoresist (which defines a line pattern) are formed on top. The line pattern from the photoresist is transferred down into the dielectric material, creating a line opening above the via, but leaving some of the OPL and sacrificial material at the bottom of the via. These remaining OPL and sacrificial material portions are then removed, creating a combined via/line opening. Finally, a metal or metal alloy is deposited into this combined opening to form the interconnect.
2. The method of claim 1 , wherein an angle alpha, α, as measured from an outside vertical sidewall of said bottom portion of said via opening to a bottom horizontal surface of said line opening is from 90° to 110°.
The method described above (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal) creates a specific angle in the structure. The angle (alpha) measured from the outside vertical wall of the bottom part of the via to the bottom horizontal surface of the line opening, is between 90 and 110 degrees.
3. The method of claim 1 , further comprising another interconnect dielectric material layer located beneath said interconnect dielectric material layer, wherein an interconnect metal or metal alloy is embedded in said another interconnect dielectric material, wherein said via opening exposes a surface of said interconnect metal or metal alloy embedded in said another dielectric material layer, and wherein an angle beta, β, as measured from an outside vertical sidewall of said bottom portion of said via opening to a topmost horizontal surface of said interconnect metal or metal alloy is from 70° to 90°.
In the method described above (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal), there's another dielectric layer located beneath the first one. This lower layer contains a metal interconnect. The via created in the first dielectric exposes the surface of this lower metal interconnect. The angle (beta) measured from the outside vertical wall of the bottom of the via to the top surface of the exposed metal interconnect in the lower dielectric layer is between 70 and 90 degrees.
4. The method of claim 2 , further comprising a dielectric capping layer separating said interconnect dielectric material layer from said another interconnect dielectric material layer, wherein said via opening extends through said dielectric capping layer.
Referring to the method where the angle alpha between the via and line opening sidewalls is between 90 and 110 degrees (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal), a dielectric capping layer separates the upper and lower dielectric layers. The via extends completely through this capping layer to reach the underlying metal.
5. The method of claim 1 , further comprising a hard mask layer located directly on a topmost surface of said interconnect dielectric layer, wherein said via opening extends through said hard mask layer.
In the method described above (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal), a hard mask layer is present directly on top of the upper dielectric layer. The via extends through this hard mask layer.
6. The method of claim 1 , wherein said continuous layer of sacrificial material comprises a dielectric or metallic oxide or nitride.
In the method described above (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal), the continuous layer of sacrificial material lining the via is composed of a dielectric or metallic oxide or nitride. Example materials are silicon dioxide, silicon nitride, or titanium nitride.
7. The method of claim 1 , wherein said material stack further comprises a hard mask layer located between said OPL and said patterned photoresist.
In the method described above (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal), the material stack (OPL and patterned photoresist) also includes a hard mask layer positioned between the OPL and the photoresist. This hard mask helps in transferring the line pattern.
8. The method of claim 1 , wherein a topmost surface of said portion of said OPL and said portion of said continuous layer of sacrificial material that remain within said lower portion of the via opening after said transferring are coplanar with a bottom horizontal surface of said line opening.
In the method described above (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal), after transferring the line pattern and before removing the remaining OPL/sacrificial material, the top surface of the remaining OPL and sacrificial material are at the same level as the bottom surface of the newly formed line opening. They are coplanar.
9. The method of claim 1 , wherein said forming said interconnect metal or metal alloy comprises: forming a continuous layer of a diffusion barrier material; forming a layer of an interconnect metal or metal alloy on said continuous layer of said diffusion barrier material; and removing portions of said layer of said interconnect metal or metal alloy and portions of continuous layer of said diffusion barrier material that are present outside said combined via opening and line opening.
In the method described above (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal), forming the metal interconnect involves these steps: First, a thin, continuous layer of a diffusion barrier material is deposited to prevent metal diffusion. Next, the metal (or metal alloy) is deposited on top of the diffusion barrier. Finally, any excess metal and diffusion barrier material outside the combined via/line opening is removed, leaving the interconnect only within the desired area.
10. The method of claim 1 , wherein said transferring said line pattern to said upper portion of said interconnect dielectric material layer comprises one or more etching processes.
In the method described above (creating a via opening in a dielectric, lining with sacrificial material, forming OPL and patterned photoresist, transferring the line pattern, removing remaining OPL/sacrificial material, and filling with metal), the process of transferring the line pattern from the photoresist into the dielectric material is done by one or more etching steps.
11. A semiconductor structure comprising: an interconnect dielectric material layer containing a combined via opening/line opening, wherein an angle alpha, α, as measured from an outside vertical sidewall of said via opening to a bottom horizontal surface of said line opening is from 90° to 110°; and another interconnect dielectric material layer located beneath said interconnect dielectric material layer, wherein an interconnect metal or metal alloy is embedded in said another interconnect dielectric material, wherein said via opening exposes a surface of said interconnect metal or metal alloy embedded in said another dielectric material layer, and wherein an angle beta, β, as measured from an outside vertical sidewall of said via opening to a topmost horizontal surface of said interconnect metal or metal alloy is from 70° to 90°.
A semiconductor structure features an interconnect dielectric material with a combined via/line opening. The angle (alpha) from the via's sidewall to the bottom of the line opening is between 90 and 110 degrees. Below this layer is another interconnect dielectric layer containing a metal interconnect. The via exposes the surface of this lower metal. The angle (beta) from the via's sidewall to the top surface of the lower metal is between 70 and 90 degrees. This design allows for controlled electrical connections between layers.
12. The semiconductor structure of claim 11 , further comprising a diffusion barrier liner lining an entirety of said combined via opening/line opening.
The semiconductor structure with a combined via/line opening where the via/line opening has specific angles (alpha between 90-110 degrees and beta between 70-90 degrees) also includes a diffusion barrier liner that coats the entire inside surface of the combined via/line opening.
13. The semiconductor structure of claim 12 , further comprising an interconnect metal or metal alloy located on an exposed surface of said diffusion barrier liner and present in said combined via opening/line opening.
Building upon the semiconductor structure having a combined via/line opening with defined angles (alpha between 90-110 degrees and beta between 70-90 degrees) and the diffusion barrier liner covering the via/line opening surfaces, an interconnect metal or metal alloy is placed on the exposed surface of the diffusion barrier liner and fills the combined via/line opening.
14. The semiconductor structure of claim 13 , wherein a topmost surface of each of said diffusion barrier liner and said interconnect metal or metal alloy is coplanar with each other and coplanar with a topmost surface of said interconnect dielectric material layer.
In the semiconductor structure with a combined via/line opening with defined angles (alpha between 90-110 degrees and beta between 70-90 degrees) covered with diffusion barrier liner and filled with metal, the top surfaces of the diffusion barrier liner and the metal are at the same height and also at the same height as the top surface of the surrounding dielectric material. They are coplanar.
15. The semiconductor structure of claim 11 , further comprising a dielectric capping layer separating said interconnect dielectric material layer from said another interconnect dielectric material layer, wherein said via opening extends through said dielectric capping layer.
The semiconductor structure featuring a combined via/line opening with defined angles (alpha between 90-110 degrees and beta between 70-90 degrees) also has a dielectric capping layer positioned between the upper and lower dielectric layers. The via extends through this capping layer.
16. The semiconductor structure of claim 11 , further comprising another line opening located in said interconnect dielectric material layer and adjacent to said combined via opening/line opening.
The semiconductor structure featuring a combined via/line opening with defined angles (alpha between 90-110 degrees and beta between 70-90 degrees) further comprises another line opening located in the same dielectric layer and positioned adjacent to the combined via/line opening.
17. The semiconductor structure of claim 16 , wherein said another line opening contains a diffusion barrier liner lining an entirety of said line opening, and an interconnect metal or metal alloy located on an exposed surface of said diffusion barrier liner and present in said line opening.
Building upon the semiconductor structure having a combined via/line opening with defined angles (alpha between 90-110 degrees and beta between 70-90 degrees) and an additional adjacent line opening, this additional line opening has a diffusion barrier liner coating its entire inside surface, and an interconnect metal or metal alloy filling the remaining space on top of the liner.
18. The semiconductor structure of claim 11 , wherein said interconnect metal or metal alloy comprises copper (Cu), a copper-aluminum alloy (Cu—Al), a copper-manganese alloy (Cu—Mn), aluminum (Al), or an aluminum-copper alloy (Al—Cu).
In the semiconductor structure featuring a combined via/line opening with defined angles (alpha between 90-110 degrees and beta between 70-90 degrees), the interconnect metal or metal alloy can be made of copper (Cu), a copper-aluminum alloy (Cu—Al), a copper-manganese alloy (Cu—Mn), aluminum (Al), or an aluminum-copper alloy (Al—Cu).
19. The semiconductor structure of claim 11 , wherein said via opening of said combined via opening/line opening is located directly beneath said line opening of said combined via opening/line opening.
The semiconductor structure featuring a combined via/line opening with defined angles (alpha between 90-110 degrees and beta between 70-90 degrees) has the via portion of the combined via/line opening located directly underneath the line opening portion.
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August 16, 2016
September 26, 2017
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