A via opening is provided in an interconnect dielectric material. Prior to line opening formation, a continuous layer of a sacrificial material is formed lining the entirety of the via opening. An organic planarization layer (OPL) and a photoresist that contains a line pattern are formed above the interconnect dielectric material. The line pattern is then transferred into an upper portion of the interconnect dielectric material, while maintaining a portion of the OPL and a portion of the continuous layer of sacrificial material within a lower portion of the via opening. The remaining portions of the OPL and the sacrificial material are then removed from the bottom portion of the via opening. A combined via opening/line opening is provided in which the via opening has a well controlled profile/geometry. An interconnect metal or metal alloy can then be formed into the combined via opening/line opening.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor structure, said method comprising: forming a via opening in an interconnect dielectric material layer; forming a continuous layer of a sacrificial material lining the entirety of said via opening; forming a material stack comprising an organic planarization layer (OPL) and a patterned photoresist above said interconnect dielectric material layer, wherein a portion of said OPL fills a remaining volume of said via opening, and wherein said patterned photoresist contains a line pattern that is present directly above said via opening; transferring said line pattern to an upper portion of said interconnect dielectric material layer, wherein a portion of said OPL and a portion of said continuous layer of sacrificial material remain within a lower portion of the via opening after said transferring; removing said remaining portions of said OPL and said sacrificial material from said bottom portion of said via opening after said transferring to provide a combined via opening/line opening; and forming an interconnect metal or metal alloy within said combined via opening/line opening.
2. The method of claim 1 , wherein an angle alpha, α, as measured from an outside vertical sidewall of said bottom portion of said via opening to a bottom horizontal surface of said line opening is from 90° to 110°.
3. The method of claim 1 , further comprising another interconnect dielectric material layer located beneath said interconnect dielectric material layer, wherein an interconnect metal or metal alloy is embedded in said another interconnect dielectric material, wherein said via opening exposes a surface of said interconnect metal or metal alloy embedded in said another dielectric material layer, and wherein an angle beta, β, as measured from an outside vertical sidewall of said bottom portion of said via opening to a topmost horizontal surface of said interconnect metal or metal alloy is from 70° to 90°.
4. The method of claim 2 , further comprising a dielectric capping layer separating said interconnect dielectric material layer from said another interconnect dielectric material layer, wherein said via opening extends through said dielectric capping layer.
5. The method of claim 1 , further comprising a hard mask layer located directly on a topmost surface of said interconnect dielectric layer, wherein said via opening extends through said hard mask layer.
6. The method of claim 1 , wherein said continuous layer of sacrificial material comprises a dielectric or metallic oxide or nitride.
7. The method of claim 1 , wherein said material stack further comprises a hard mask layer located between said OPL and said patterned photoresist.
8. The method of claim 1 , wherein a topmost surface of said portion of said OPL and said portion of said continuous layer of sacrificial material that remain within said lower portion of the via opening after said transferring are coplanar with a bottom horizontal surface of said line opening.
9. The method of claim 1 , wherein said forming said interconnect metal or metal alloy comprises: forming a continuous layer of a diffusion barrier material; forming a layer of an interconnect metal or metal alloy on said continuous layer of said diffusion barrier material; and removing portions of said layer of said interconnect metal or metal alloy and portions of continuous layer of said diffusion barrier material that are present outside said combined via opening and line opening.
10. The method of claim 1 , wherein said transferring said line pattern to said upper portion of said interconnect dielectric material layer comprises one or more etching processes.
11. A semiconductor structure comprising: an interconnect dielectric material layer containing a combined via opening/line opening, wherein an angle alpha, α, as measured from an outside vertical sidewall of said via opening to a bottom horizontal surface of said line opening is from 90° to 110°; and another interconnect dielectric material layer located beneath said interconnect dielectric material layer, wherein an interconnect metal or metal alloy is embedded in said another interconnect dielectric material, wherein said via opening exposes a surface of said interconnect metal or metal alloy embedded in said another dielectric material layer, and wherein an angle beta, β, as measured from an outside vertical sidewall of said via opening to a topmost horizontal surface of said interconnect metal or metal alloy is from 70° to 90°.
12. The semiconductor structure of claim 11 , further comprising a diffusion barrier liner lining an entirety of said combined via opening/line opening.
13. The semiconductor structure of claim 12 , further comprising an interconnect metal or metal alloy located on an exposed surface of said diffusion barrier liner and present in said combined via opening/line opening.
14. The semiconductor structure of claim 13 , wherein a topmost surface of each of said diffusion barrier liner and said interconnect metal or metal alloy is coplanar with each other and coplanar with a topmost surface of said interconnect dielectric material layer.
15. The semiconductor structure of claim 11 , further comprising a dielectric capping layer separating said interconnect dielectric material layer from said another interconnect dielectric material layer, wherein said via opening extends through said dielectric capping layer.
16. The semiconductor structure of claim 11 , further comprising another line opening located in said interconnect dielectric material layer and adjacent to said combined via opening/line opening.
17. The semiconductor structure of claim 16 , wherein said another line opening contains a diffusion barrier liner lining an entirety of said line opening, and an interconnect metal or metal alloy located on an exposed surface of said diffusion barrier liner and present in said line opening.
18. The semiconductor structure of claim 11 , wherein said interconnect metal or metal alloy comprises copper (Cu), a copper-aluminum alloy (Cu—Al), a copper-manganese alloy (Cu—Mn), aluminum (Al), or an aluminum-copper alloy (Al—Cu).
19. The semiconductor structure of claim 11 , wherein said via opening of said combined via opening/line opening is located directly beneath said line opening of said combined via opening/line opening.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 16, 2016
September 26, 2017
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